DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “wherein the second substrate and the first element layer stack up in a direction perpendicular or substantially perpendicular to a surface of the first substrate, and wherein the first through electrode and each of the first transistor and the capacitor overlap each other” recited in claim 2 and the “wherein the first through electrode and each of the first transistor and the magnetic tunnel junction element overlap each other” recited in claim 3 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 8 and 12 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 8 and 12, both claims recite the limitation “a first peripheral circuit over the first substrate” (emphasis added) which does not have support in the disclosure. The specification discloses, in ¶ [0034], that “the peripheral circuit 20 provided in the substrate 25” (emphasis added). Figs. 1A, 3B, and 6B also depict the peripheral circuit 20 provided in, rather than over, the substrate 25.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, and 8-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yokoyama et al. (US 20180240797 A1) herein after “Yokoyama” in view of Yamazaki et al. (US 20190006386 A1) herein after “Yamazaki”.
Regarding claim 1, Figs. 4 and 13 of Yokoyama disclose a semiconductor device (Fig. 13, semiconductor device 4, ¶ [0110]) comprising:
a first substrate (Fig. 13, semiconductor substrate 71, ¶ [0087]);
a second substrate (Fig. 13, semiconductor substrate 10, ¶ [0073]) over the first substrate (71);
a first element layer (see Annotation 1, Fig. 13 of Yokoyama, “EL1”) over and in contact with the second substrate (10); and
a first through electrode (Fig. 13, contact plug P.sub.1, conductive layer 34, ¶ [0076] and [0110]) in the second substrate (10) and the first element layer (EL1),
wherein the first element layer (EL1) comprises:
a first transistor (Fig. 4, transistor 20, ¶ [0073]) in the first element layer (EL1) (shown in Fig. 13);
a first electrode (Fig. 13, metal film M1, ¶ [0080]) electrically connected to the first through electrode (P1, 34);
a second electrode (Fig. 13, vias V1-V3, ¶ [0081]); and
a third electrode (Fig. 13, metal film M3′, ¶ [0088]) on a surface of the first element layer (EL1),
wherein the third electrode (M3’) is electrically connected to the first electrode (M1) via the second electrode (V1-V3),
wherein the first transistor (20) comprises a semiconductor layer (“a Si-planar transistor 20”, ¶ [0072]),
wherein the first through electrode (P1, 34) is exposed on a surface of the second substrate (10),
wherein the first through electrode (P1, 34) is electrically connected to the first electrode (M1),
wherein the second substrate (10) and the first element layer (EL1) stack up in a direction (vertical direction in Fig. 13) perpendicular or substantially perpendicular to a surface of the first substrate (71), and
wherein the first transistor (20) and the first through electrode (P1, 34) overlap each other (The first transistor and first through electrode overlap within insulating film 27).
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Annotation 1, Fig. 13 of Yokoyama
Yokoyama fails to disclose the semiconductor layer comprising a metal oxide in a channel formation region.
In the similar field of endeavor of semiconductor storage devices, Fig. 5 of Yamazaki discloses a semiconductor layer (Fig. 3A, oxide 704, ¶ [0133]) comprising a metal oxide in a channel formation region (“a metal oxide used in an active layer of a transistor”, “In the oxide 704, a region 734 that is positioned in the same layer as the conductor 701_k serves as a channel formation region”, ¶ [0129] and [0143]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor layer of Yokoyama with the metal oxide as disclosed by Yamazaki, to achieve more favorable on-state characteristics and higher mobility (see Yamazaki, ¶ [0165]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 2, Figs. 4 and 13 of Yokoyama disclose a semiconductor device (4) comprising:
a first substrate (71);
a second substrate (10) over the first substrate (71);
a first element layer (EL1) in contact with the second substrate (10); and
a first through electrode (P1, 34) in the second substrate (10) and the first element layer (EL1),
wherein the first element layer (EL1) comprises:
a first memory cell (20, 30) in the first element layer (EL1);
a first electrode (M1) electrically connected to the first through electrode (P1, 34);
a second electrode (V1-V3); and
a third electrode (M3’) on a surface of the first element layer (EL1),
wherein the first electrode (M1) is electrically connected to the first through electrode (P1, 34),
wherein the third electrode (M3’) is electrically connected to the first electrode (M1) via the second electrode (V1-V3),
wherein the first memory cell (20, 30) comprises a first transistor (20) and a capacitor (30),
wherein the first transistor (20) comprises a semiconductor layer (“a Si-planar transistor 20”, ¶ [0072]),
wherein the first through electrode (P1, 34) is exposed on a surface of the second substrate (10),
wherein the second substrate (10) and the first element layer (EL1) stack up in a direction (vertical in Fig. 13) perpendicular or substantially perpendicular to a surface of the first substrate (71), and wherein the first through electrode (P1, 34) and each of the first transistor (20) and the capacitor (30) are provided in a region overlapping with the first through electrode (P1, 34) (the first transistor and first through electrode overlap within insulating film 27 and the capacitor and first through electrode overlap within insulating layer 63A) and overlap each other (the first transistor and the capacitor overlap in the vertical direction as shown in Fig. 13).
Yokoyama fails to disclose the semiconductor layer comprising a metal oxide in a channel formation region.
In the similar field of endeavor of semiconductor storage devices, Fig. 5 of Yamazaki discloses a semiconductor layer (704) comprising a metal oxide in a channel formation region (“a metal oxide used in an active layer of a transistor”, “In the oxide 704, a region 734 that is positioned in the same layer as the conductor 701_k serves as a channel formation region”, ¶ [0129] and [0143]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor layer of Yokoyama with the metal oxide as disclosed by Yamazaki, to achieve more favorable on-state characteristics and higher mobility (see Yamazaki, ¶ [0165]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 3, Figs. 4 and 13 of Yokoyama disclose a semiconductor device (4) comprising:
a first substrate (71);
a second substrate (10) over the first substrate (71);
a first element layer (EL1) over and in contact with the second substrate (10); and
a first through electrode (P1, 34) in the second substrate (10) and the first element layer (EL1),
wherein the first element layer (EL1) comprises:
a first memory cell (20, 30) in the first element layer (EL1);
a first electrode (M1) electrically connected to the first through electrode (P1, 34);
a second electrode (V1-V3); and
a third electrode (M3’) on a surface of the first element layer (EL1),
wherein the third electrode (M3’) is electrically connected to the first electrode (M1) via the second electrode (V1-V3),
wherein the first memory cell (20, 30) comprises a first transistor (20) and a magnetic tunnel junction element (30),
wherein the first transistor (20) comprises a semiconductor layer (“a Si-planar transistor 20”, ¶ [0072]),
wherein the first through electrode (P1, 34) is exposed on a surface of the second substrate (10),
wherein the second substrate (10) and the first element layer (EL1) stack up in a direction (vertical in Fig. 13) perpendicular or substantially perpendicular to a surface of the first substrate (71), and
wherein the first through electrode (P1, 34) and each of the first transistor (20) and the magnetic tunnel junction element (30) overlap each other (the first transistor and first through electrode overlap within insulating film 27 and the magnetic tunnel junction element and first through electrode overlap within insulating layer 63A, and the first transistor and the magnetic tunnel junction element overlap in the vertical direction as shown in Fig. 13).
Yokoyama fails to disclose the semiconductor layer comprising a metal oxide in a channel formation region.
In the similar field of endeavor of semiconductor storage devices, Fig. 5 of Yamazaki discloses a semiconductor layer (704) comprising a metal oxide in a channel formation region (“a metal oxide used in an active layer of a transistor”, “In the oxide 704, a region 734 that is positioned in the same layer as the conductor 701_k serves as a channel formation region”, ¶ [0129] and [0143]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor layer of Yokoyama with the metal oxide as disclosed by Yamazaki, to achieve more favorable on-state characteristics and higher mobility (see Yamazaki, ¶ [0165]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 4, Yokoyama and Yamazaki together disclose the semiconductor device according to claim 3 as applied above, and Fig. 14 of Yokoyama further discloses wherein the magnetic tunnel junction element (30) comprises a stacked-layer structure of an unfixed layer (Fig. 14, storage layer 32D, ¶ [0115]), an insulating layer (Fig. 14, insulating layer 32C, ¶ [0115]) and a fixed layer (Fig. 14, magnetization fixed layer 32B, ¶ [0115]).
Regarding claim 8, Yokoyama and Yamazaki together disclose the semiconductor device according to claim 1 as applied above, and Figs. 12-13 of Yokoyama further discloses comprising a first peripheral circuit (110) over the first substrate (71) to drive the first transistor (20) (“The transistor 70 having a fin-FET structure as a transistor configuring the logic circuit 110 and the data processor 120 is provided in the first substrate 100”, ¶ [0085]).
Regarding claim 9, Yokoyama and Yamazaki together disclose the semiconductor device according to claim 1 as applied above, and Fig. 13 of Yokoyama further discloses wherein the second electrode (V1-V3) is provided in a layer where an electrode connected to the first transistor (20) is provided (the first transistor is connected to the via layers by connection unit 28C).
Regarding claim 10, Yokoyama and Yamazaki together disclose the semiconductor device according to claim 1 as applied above, and Fig. 13 of Yokoyama further discloses wherein the second substrate (10) is a silicon substrate (“The semiconductor layer 10S2 includes, for example, single-crystal silicon”, ¶ [0075]).
Regarding claim 11, Yokoyama and Yamazaki together disclose the semiconductor device according to claim 1 as applied above, but Yokoyama fails to disclose wherein the metal oxide comprises In, Ga and Zn.
In the similar field of endeavor of semiconductor storage devices, Fig. 5 of Yamazaki discloses wherein the metal oxide comprises In, Ga and Zn (“the oxide 704, a metal oxide such as an In-M-Zn oxide (M is one or more of…, gallium”, ¶ [0166]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor layer of Yokoyama with the metal oxide as disclosed by Yamazaki, to achieve more favorable on-state characteristics and higher mobility (see Yamazaki, ¶ [0165]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 12, Yokoyama and Yamazaki together disclose the semiconductor device according to claim 3 as applied above, and Fig. 13 of Yokoyama further discloses comprising a first peripheral circuit (110) over the first substrate (71) to drive the first transistor (20).
Regarding claim 13, Yokoyama and Yamazaki together disclose the semiconductor device according to claim 2 as applied above, and Fig. 13 of Yokoyama further discloses wherein the second substrate (10) is a silicon substrate (“The semiconductor layer 10S2 includes, for example, single-crystal silicon”, ¶ [0075]).
Regarding claim 14, Yokoyama and Yamazaki together disclose the semiconductor device according to claim 2 as applied above, but Yokoyama fails to disclose wherein the metal oxide comprises In, Ga and Zn.
In the similar field of endeavor of semiconductor storage devices, Fig. 5 of Yamazaki discloses wherein the metal oxide comprises In, Ga and Zn (“the oxide 704, a metal oxide such as an In-M-Zn oxide (M is one or more of…, gallium”, ¶ [0166]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor layer of Yokoyama with the metal oxide as disclosed by Yamazaki, to achieve more favorable on-state characteristics and higher mobility (see Yamazaki, ¶ [0165]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 15, Yokoyama and Yamazaki together disclose the semiconductor device according to claim 3 as applied above, and Fig. 13 of Yokoyama further discloses wherein the second substrate (10) is a silicon substrate (“The semiconductor layer 10S2 includes, for example, single-crystal silicon”, ¶ [0075]).
Regarding claim 16, Yokoyama and Yamazaki together disclose the semiconductor device according to claim 3 as applied above, but Yokoyama fails to disclose wherein the metal oxide comprises In, Ga and Zn.
In the similar field of endeavor of semiconductor storage devices, Fig. 5 of Yamazaki discloses wherein the metal oxide comprises In, Ga and Zn (“the oxide 704, a metal oxide such as an In-M-Zn oxide (M is one or more of…, gallium”, ¶ [0166]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor layer of Yokoyama with the metal oxide as disclosed by Yamazaki, to achieve more favorable on-state characteristics and higher mobility (see Yamazaki, ¶ [0165]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Claims 5-7, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yokoyama (US 20180240797 A1) in view of Yamazaki (US 20190006386 A1) and Kajigaya (US 20130070506 A1).
Regarding claim 5, Figs. 4 and 13 of Yokoyama disclose a semiconductor device (4) comprising:
a first substrate (71);
a second substrate (10) over the first substrate (71);
a first element layer (EL1) over and in contact with the second substrate (10); and
a first through electrode (P1, 34) in the second substrate (10) and the first element layer (EL1),
wherein the first element layer (EL1) comprises:
a first plurality of memory cells (20, 30);
a first circuit (Fig. 12, logic circuit 110, ¶ [0067]);
a first electrode (M1) electrically connected to the first through electrode (P1, 34);
a second electrode (V1-V3); and
a third electrode (M3’) on a surface of the first element layer (EL1),
wherein the third electrode (M3’) is electrically connected to the first electrode (M1) via the second electrode (V1-V3),
wherein the first plurality of memory cells (20, 30) and the first circuit (110) each comprise a transistor (Fig. 13, transistor 70, ¶ [0072]),
wherein the first through electrode (P1, 34) is exposed on a surface of the second substrate (10),
wherein the second substrate (10) and the first element layer (EL1) stack up in a direction (vertical in Fig. 13) perpendicular or substantially perpendicular to a surface of the first substrate (71), and
wherein the first through electrode (P1, 34) and the transistor (70) of the first circuit (110) overlap each other (the first through electrode and the transistor overlap in the vertical direction).
Yokoyama fails to disclose the transistors comprising a metal oxide in a channel formation region.
In the similar field of endeavor of semiconductor storage devices, Fig. 5 of Yamazaki discloses the transistor (MT) in the first plurality of memory cells comprising a metal oxide in a channel formation region (“a metal oxide used in an active layer of a transistor”, “In the oxide 704, a region 734 that is positioned in the same layer as the conductor 701_k serves as a channel formation region”, ¶ [0129] and [0143]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transistor of Yokoyama with the metal oxide as disclosed by Yamazaki, to achieve more favorable on-state characteristics and higher mobility (see Yamazaki, ¶ [0165]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Yamazaki fails to disclose the transistor in the first circuit comprising a metal oxide in a channel formation region.
In the similar field of endeavor of memory cells, Kajigaya discloses the transistor (“the sense amplifier including a second transistor”, ¶ [0015]) in the first circuit (Fig. 2, local sense amplifier LSA, ¶ [0042]) comprising a metal oxide in a channel formation region (“MOSFETs (the second transistors)”, ¶ [0039]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transistor of Yokoyama with the metal oxide as disclosed by Kajigaya, to achieve desired carrier mobility (see Kajigaya, ¶ [0016]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 6, Yokoyama, Yamazaki and Kajigaya together disclose the semiconductor device according to claim 5 as applied above, but Yokoyama and Yamazaki fail to disclose wherein one of the first plurality of memory cells is electrically connected to one of a plurality of bit lines, and
wherein the first circuit is configured to select any one of the plurality of bit lines and amplify and output a potential of the selected bit line.
In the similar field of endeavor of memory cells, Fig. 2 of Kajigaya discloses wherein one of the first plurality of memory cells (Fig. 2, plurality of memory cells MC, ¶ [0036]) is electrically connected to one of a plurality of bit lines (Fig. 2, local bit lines LBL, ¶ [0036]), and
wherein the first circuit (LSA) is configured to select any one of the plurality of bit lines (LBL) and amplify and output a potential of the selected bit line (“This structure enables the local sense amplifier LSA to sense and amplify the signal on a selected local bit line LBL”, ¶ [0043]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor device of Yokoyama with the first circuit as disclosed by Kajigaya, to allow selective reading of the memory cell array (see Kajigaya, ¶ [0042]).
Regarding claim 7, Yokoyama, Yamazaki and Kajigaya together disclose the semiconductor device according to claim 5 as applied above, but Yokoyama and Yamazaki fail to disclose wherein each of the first plurality of memory cells is electrically connected to a word line, and
wherein the first circuit is configured to amplify a signal supplied to the word line.
In the similar field of endeavor of memory cells, Fig. 2 of Kajigaya discloses wherein each of the first plurality of memory cells (MC) is electrically connected to a word line (WL), and
wherein the first circuit (LSA) is configured to amplify a signal supplied to the word line (WL) (“data of the memory cell MC corresponding to the selected word line WL is read out to the local bit line LBL, and is inputted to the local sense amplifier LSA”, ¶ [0049]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor device of Yokoyama with the first circuit as disclosed by Kajigaya, to allow selective reading of the memory cell array (see Kajigaya, ¶ [0042]).
Regarding claim 17, Yokoyama, Yamazaki and Kajigaya together disclose the semiconductor device according to claim 5 as applied above, and Fig. 13 of Yokoyama further discloses wherein the second substrate (10) is a silicon substrate (“The semiconductor layer 10S2 includes, for example, single-crystal silicon”, ¶ [0075]).
Regarding claim 18, Yokoyama, Yamazaki and Kajigaya together disclose the semiconductor device according to claim 5 as applied above, but Yokoyama and Kajigaya fail to disclose wherein the metal oxide comprises In, Ga and Zn.
In the similar field of endeavor of semiconductor storage devices, Fig. 5 of Yamazaki discloses wherein the metal oxide comprises In, Ga and Zn (“the oxide 704, a metal oxide such as an In-M-Zn oxide (M is one or more of…, gallium”, ¶ [0166]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor layer of Yokoyama with the metal oxide as disclosed by Yamazaki, to achieve more favorable on-state characteristics and higher mobility (see Yamazaki, ¶ [0165]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Conclusion
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/C.A.N./ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893