DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed June 10, 2026. Claims 1-3, 5, 8, and 12 have been amended. No claims have been added. No claims have been canceled. Currently, claims 1-18 are pending.
Applicant’s Amendments to claims 8 and 12 overcome the 112(a) rejections outlined in the previous Office Action. The 112(a) rejections of claims 8 and 12 have been withdrawn.
Response to Arguments
Applicant’s arguments with respect to claims 1-3 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments with respect to claim 5 have been fully considered but they are not persuasive.
Applicant asserts that amending claim 1 to include the limitation “wherein the region penetrating the second substrate and the transistor of the first circuit overlap each other” overcomes Yokoyama because the narrow region of the contact plug P1 does not overlap transistor 20.
The Examiner disagrees that Yokoyama does not disclose the limitations of newly amended claim 5. The claim requires that the region penetrating the second substrate be overlapping the transistor of the first circuit. As outlined on page 15 of the previous Office Action, the transistor of the first circuit in Yokoyama is transistor 70, while transistor 20 is the transistor of the memory cell. Therefore, Fig. 13 of Yokoyama discloses wherein the region penetrating the second substrate (10) and the transistor (70) of the first circuit (110) overlap each other (the first through electrode and the transistor overlap in the vertical direction) and the rejection of claim 5 is maintained and presented herein as appropriate.
Applicant’s arguments with respect to the drawing objections outlined in the previous Office Action are persuasive. The drawing objections have been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, and 8-16 are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 20200350014 A1) in view of Yokoyama et al. (US 20180240797 A1) herein after “Yokoyama” and Yamazaki et al. (US 20190006386 A1) herein after “Yamazaki”.
Regarding claim 1, Fig. 4 of Liu discloses a semiconductor device (Fig. 4, memory device 400, ¶ [0055]) comprising:
a first substrate (Fig. 4, substrate 408, ¶ [0056]);
a second substrate (Fig. 4, semiconductor layer 440, interconnect layer 452, ¶ [0062]) over the first substrate (408);
a first element layer (Fig. 4, device layer 438, ¶ [0061]) over and in contact with the second substrate (440, 452); and
a first through electrode (Fig. 4, contact pads 454, contacts 456, ¶ [0062]) in the second substrate (440, 452) and the first element layer (438),
wherein the first element layer (438) comprises:
a first transistor (Fig. 4, DRAM selection transistor 448, ¶ [0060]);
wherein the first through electrode (454, 456) is exposed on a surface of the second substrate (440, 452),
wherein the first through electrode (454, 456) comprises a region (see Annotation 1, Fig. 4 of Liu, R1) penetrating the second substrate (440, 452),
wherein the first through electrode (454, 456) is electrically connected to the first electrode (451),
wherein the second substrate (440, 452) and the first element layer (438) stack up in a direction perpendicular or substantially perpendicular to a surface of the first substrate (408), and
wherein the first transistor (448) and the region (R1) penetrating the second substrate (440, 452) overlap each other.
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Annotation 1, Fig. 4 of Liu
Liu discloses the first through electrode being electrically connected to subsequent interconnect layers (see ¶ [0062]), but Liu fails to explicitly disclose a first electrode electrically connected to the first through electrode;
a second electrode; and
a third electrode on a surface of the first element layer,
wherein the third electrode is electrically connected to the first electrode via the second electrode,
wherein the first transistor comprises a semiconductor layer comprising a metal oxide in a channel formation region.
In the similar field of endeavor of semiconductor integrated circuit devices, Fig. 13 of Yokoyama discloses a first electrode (Fig. 13, metal film M1, ¶ [0080]) electrically connected to the first through electrode (Fig. 13, contact plug P.sub.1, conductive layer 34, ¶ [0076] and [0110]);
a second electrode (Fig. 13, vias V1-V3, ¶ [0081]); and
a third electrode (Fig. 13, metal film M3′, ¶ [0088]) on a surface of the first element layer,
wherein the third electrode (M3’) is electrically connected to the first electrode (M1) via the second electrode (V1-V3).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor layer of Liu with the interconnect structure as disclosed by Yokoyama, to provide connection to subsequent layers (see Yokoyama, ¶ [0088]).
Yokoyama fails to disclose the semiconductor layer comprising a metal oxide in a channel formation region.
In the similar field of endeavor of semiconductor storage devices, Fig. 5 of Yamazaki discloses a semiconductor layer (Fig. 3A, oxide 704, ¶ [0133]) comprising a metal oxide in a channel formation region (“a metal oxide used in an active layer of a transistor”, “In the oxide 704, a region 734 that is positioned in the same layer as the conductor 701_k serves as a channel formation region”, ¶ [0129] and [0143]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor layer of Yokoyama with the metal oxide as disclosed by Yamazaki, to achieve more favorable on-state characteristics and higher mobility (see Yamazaki, ¶ [0165]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 2, Fig. 4 of Liu discloses a semiconductor device (400) comprising:
a first substrate (408);
a second substrate (440, 452) over the first substrate (408);
a first element layer (438) in contact with the second substrate (440, 452); and
a first through electrode (454, 456) in the second substrate (440, 452) and the first element layer (438),
wherein the first element layer (438) comprises:
a first memory cell (Fig. 4, DRAM cell 444, ¶ [0060]);
wherein the first memory cell (444) comprises a first transistor (448) and a capacitor (Fig. 4, capacitor 450, ¶ [0060]),
wherein the first through electrode (454, 456) is exposed on a surface of the second substrate (440, 452),
wherein the first through electrode (454, 456) comprises a region (R1) penetrating the second substrate (440, 452),
wherein the second substrate (440, 452) and the first element layer (438) stack up in a direction perpendicular or substantially perpendicular to a surface of the first substrate (408), and
wherein the region (R1) penetrating the second substrate (440, 452) and each of the first transistor (448) and the capacitor (450) overlap each other.
Liu discloses the first through electrode being electrically connected to subsequent interconnect layers (see ¶ [0062]), but Liu fails to explicitly disclose a first electrode electrically connected to the first through electrode;
a second electrode; and
a third electrode on a surface of the first element layer,
wherein the third electrode is electrically connected to the first electrode via the second electrode,
wherein the first transistor comprises a semiconductor layer comprising a metal oxide in a channel formation region.
In the similar field of endeavor of semiconductor integrated circuit devices, Fig. 13 of Yokoyama discloses a first electrode (M1) electrically connected to the first through electrode (P1, 34);
a second electrode (V1-V3); and
a third electrode (M3’) on a surface of the first element layer,
wherein the first electrode (M1) is electrically connected to the first through electrode (P1, 34),
wherein the third electrode (M3’) is electrically connected to the first electrode (M1) via the second electrode (V1-V3).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor layer of Liu with the interconnect structure as disclosed by Yokoyama, to provide connection to subsequent layers (see Yokoyama, ¶ [0088]).
Yokoyama fails to disclose the semiconductor layer comprising a metal oxide in a channel formation region.
In the similar field of endeavor of semiconductor storage devices, Fig. 5 of Yamazaki discloses a semiconductor layer (704) comprising a metal oxide in a channel formation region (“a metal oxide used in an active layer of a transistor”, “In the oxide 704, a region 734 that is positioned in the same layer as the conductor 701_k serves as a channel formation region”, ¶ [0129] and [0143]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor layer of Yokoyama with the metal oxide as disclosed by Yamazaki, to achieve more favorable on-state characteristics and higher mobility (see Yamazaki, ¶ [0165]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 3, Fig. 4 of Liu discloses a semiconductor device (400) comprising:
a first substrate (408);
a second substrate (440, 452) over the first substrate (408);
a first element layer (438) over and in contact with the second substrate (440, 452); and
a first through electrode (454, 456) in the second substrate (440, 452) and the first element layer (438),
wherein the first element layer (438) comprises:
a first memory cell (444) in the first element layer (438);
wherein the first memory cell (444) comprises a first transistor (448) and a storage element (Fig. 4, NAND memory string 416, ¶ [0056]),
wherein the first through electrode (454, 456) is exposed on a surface of the second substrate (440, 452),
wherein the first through electrode (454, 456) comprises a region (R1) penetrating the second substrate (440, 452),
wherein the second substrate (440, 452) and the first element layer (438) stack up in a direction perpendicular or substantially perpendicular to a surface of the first substrate (408), and
wherein the region (R1) penetrating the second substrate (440, 452) and each of the first transistor (448) and the storage element (416) overlap each other.
Liu fails to disclose that the storage element is a magnetic tunnel junction element;
a first electrode electrically connected to the first through electrode;
a second electrode; and
a third electrode on a surface of the first element layer,
wherein the third electrode is electrically connected to the first electrode via the second electrode,
wherein the first transistor comprises a semiconductor layer comprising a metal oxide in a channel formation region.
In the similar field of endeavor of semiconductor integrated circuit devices, Fig. 13 of Yokoyama discloses the storage element is a magnetic tunnel junction element (“a magnetoresistance element (magnetic tunnel junction; MTJ) as the storage element 30”, ¶ [0110]);
a first electrode (M1) electrically connected to the first through electrode (P1, 34);
a second electrode (V1-V3); and
a third electrode (M3’) on a surface of the first element layer (EL1),
wherein the third electrode (M3’) is electrically connected to the first electrode (M1) via the second electrode (V1-V3).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor layer of Liu with the MTJ and interconnect structure as disclosed by Yokoyama, to increase reading and writing speed and provide connection to subsequent layers (see Yokoyama, ¶ [0088] and [0113]).
Yokoyama fails to disclose the semiconductor layer comprising a metal oxide in a channel formation region.
In the similar field of endeavor of semiconductor storage devices, Fig. 5 of Yamazaki discloses a semiconductor layer (704) comprising a metal oxide in a channel formation region (“a metal oxide used in an active layer of a transistor”, “In the oxide 704, a region 734 that is positioned in the same layer as the conductor 701_k serves as a channel formation region”, ¶ [0129] and [0143]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor layer of Yokoyama with the metal oxide as disclosed by Yamazaki, to achieve more favorable on-state characteristics and higher mobility (see Yamazaki, ¶ [0165]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 4, Liu, Yokoyama and Yamazaki together disclose the semiconductor device according to claim 3 as applied above, but Liu and Yamazaki fail to disclose wherein the magnetic tunnel junction element comprises a stacked-layer structure of an unfixed layer, an insulating layer and a fixed layer.
In the similar field of endeavor of semiconductor integrated circuit devices, Fig. 14 of Yokoyama discloses wherein the magnetic tunnel junction element (30) comprises a stacked-layer structure of an unfixed layer (Fig. 14, storage layer 32D, ¶ [0115]), an insulating layer (Fig. 14, insulating layer 32C, ¶ [0115]) and a fixed layer (Fig. 14, magnetization fixed layer 32B, ¶ [0115]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor layer of Liu with the MTJ as disclosed by Yokoyama, to increase reading and writing speed (see Yokoyama, ¶ [0113]).
Regarding claim 8, Liu, Yokoyama and Yamazaki together disclose the semiconductor device according to claim 1 as applied above, and Fig. 4 of Liu further discloses comprising a first peripheral circuit (Fig. 4, peripheral circuit 442, ¶ [0059]) in the first substrate (408) to drive the first transistor (448).
Regarding claim 9, Liu, Yokoyama and Yamazaki together disclose the semiconductor device according to claim 1 as applied above, but Liu and Yamazaki fail to disclose wherein the second electrode is provided in a layer where an electrode connected to the first transistor is provided.
In the similar field of endeavor of semiconductor integrated circuit devices, Fig. 13 of Yokoyama discloses wherein the second electrode (V1-V3) is provided in a layer where an electrode connected to the first transistor (20) is provided (the first transistor is connected to the via layers by connection unit 28C).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor layer of Liu with the interconnect structure as disclosed by Yokoyama, to provide connection to subsequent layers (see Yokoyama, ¶ [0088]).
Regarding claim 10, Liu, Yokoyama and Yamazaki together disclose the semiconductor device according to claim 1 as applied above, and Fig. 4 of Liu further discloses wherein the second substrate (440, 452) is a silicon substrate (“semiconductor layer 440 can include polysilicon”, ¶ [0061]).
Regarding claim 11, Liu, Yokoyama and Yamazaki together disclose the semiconductor device according to claim 1 as applied above, but Liu and Yokoyama fail to disclose wherein the metal oxide comprises In, Ga and Zn.
In the similar field of endeavor of semiconductor storage devices, Fig. 5 of Yamazaki discloses wherein the metal oxide comprises In, Ga and Zn (“the oxide 704, a metal oxide such as an In-M-Zn oxide (M is one or more of…, gallium”, ¶ [0166]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor layer of Liu with the metal oxide as disclosed by Yamazaki, to achieve more favorable on-state characteristics and higher mobility (see Yamazaki, ¶ [0165]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 12, Liu, Yokoyama and Yamazaki together disclose the semiconductor device according to claim 3 as applied above, and Fig. 4 of Liu further discloses comprising a first peripheral circuit (442) in the first substrate (408) to drive the first transistor (448).
Regarding claim 13, Liu, Yokoyama and Yamazaki together disclose the semiconductor device according to claim 2 as applied above, and Fig. 4 of Liu further discloses wherein the second substrate (440, 452) is a silicon substrate (“semiconductor layer 440 can include polysilicon”, ¶ [0061]).
Regarding claim 14, Liu, Yokoyama and Yamazaki together disclose the semiconductor device according to claim 2 as applied above, but Liu and Yokoyama fail to disclose wherein the metal oxide comprises In, Ga and Zn.
In the similar field of endeavor of semiconductor storage devices, Fig. 5 of Yamazaki discloses wherein the metal oxide comprises In, Ga and Zn (“the oxide 704, a metal oxide such as an In-M-Zn oxide (M is one or more of…, gallium”, ¶ [0166]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor layer of Liu with the metal oxide as disclosed by Yamazaki, to achieve more favorable on-state characteristics and higher mobility (see Yamazaki, ¶ [0165]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 15, Liu, Yokoyama and Yamazaki together disclose the semiconductor device according to claim 3 as applied above, and Fig. 4 of Liu further discloses wherein the second substrate (440, 452) is a silicon substrate (“semiconductor layer 440 can include polysilicon”, ¶ [0061]).
Regarding claim 16, Liu, Yokoyama and Yamazaki together disclose the semiconductor device according to claim 3 as applied above, but Liu and Yokoyama fail to disclose wherein the metal oxide comprises In, Ga and Zn.
In the similar field of endeavor of semiconductor storage devices, Fig. 5 of Yamazaki discloses wherein the metal oxide comprises In, Ga and Zn (“the oxide 704, a metal oxide such as an In-M-Zn oxide (M is one or more of…, gallium”, ¶ [0166]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor layer of Liu with the metal oxide as disclosed by Yamazaki, to achieve more favorable on-state characteristics and higher mobility (see Yamazaki, ¶ [0165]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Claims 5-7, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yokoyama (US 20180240797 A1) in view of Yamazaki (US 20190006386 A1) and Kajigaya (US 20130070506 A1).
Regarding claim 5, Figs. 4 and 13 of Yokoyama disclose a semiconductor device (Fig. 13, semiconductor device 4, ¶ [0110]) comprising:
a first substrate (Fig. 13, semiconductor substrate 71, ¶ [0087]);
a second substrate (Fig. 13, semiconductor substrate 10, ¶ [0073]) over the first substrate (71);
a first element layer (see Annotation 2, Fig. 13 of Yokoyama, EL1) over and in contact with the second substrate (10); and
a first through electrode (Fig. 13, contact plug P.sub.1, conductive layer 34, ¶ [0076] and [0110]) in the second substrate (10) and the first element layer (EL1),
wherein the first element layer (EL1) comprises:
a first plurality of memory cells (Fig. 4, transistor 20, ¶ [0073], Fig. 13, storage element 30, ¶ [0110]);
a first circuit (Fig. 12, logic circuit 110, ¶ [0067]);
a first electrode (M1) electrically connected to the first through electrode (P1, 34);
a second electrode (V1-V3); and
a third electrode (M3’) on a surface of the first element layer (EL1),
wherein the third electrode (M3’) is electrically connected to the first electrode (M1) via the second electrode (V1-V3),
wherein the first plurality of memory cells (20, 30) and the first circuit (110) each comprise a transistor (Fig. 4, transistor 20, ¶ [0073], Fig. 13, transistor 70, ¶ [0072]),
wherein the first through electrode (P1, 34) is exposed on a surface of the second substrate (10),
wherein the second substrate (10) and the first element layer (EL1) stack up in a direction (vertical in Fig. 13) perpendicular or substantially perpendicular to a surface of the first substrate (71), and
wherein the first through electrode (P1, 34) and the transistor (70) of the first circuit (110) overlap each other (the first through electrode and the transistor overlap in the vertical direction).
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Annotation 2, Fig. 13 of Yokoyama
Yokoyama fails to disclose the transistors comprising a metal oxide in a channel formation region.
In the similar field of endeavor of semiconductor storage devices, Fig. 5 of Yamazaki discloses the transistor (MT) in the first plurality of memory cells comprising a metal oxide in a channel formation region (“a metal oxide used in an active layer of a transistor”, “In the oxide 704, a region 734 that is positioned in the same layer as the conductor 701_k serves as a channel formation region”, ¶ [0129] and [0143]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transistor of Yokoyama with the metal oxide as disclosed by Yamazaki, to achieve more favorable on-state characteristics and higher mobility (see Yamazaki, ¶ [0165]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Yamazaki fails to disclose the transistor in the first circuit comprising a metal oxide in a channel formation region.
In the similar field of endeavor of memory cells, Kajigaya discloses the transistor (“the sense amplifier including a second transistor”, ¶ [0015]) in the first circuit (Fig. 2, local sense amplifier LSA, ¶ [0042]) comprising a metal oxide in a channel formation region (“MOSFETs (the second transistors)”, ¶ [0039]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the transistor of Yokoyama with the metal oxide as disclosed by Kajigaya, to achieve desired carrier mobility (see Kajigaya, ¶ [0016]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 6, Yokoyama, Yamazaki and Kajigaya together disclose the semiconductor device according to claim 5 as applied above, but Yokoyama and Yamazaki fail to disclose wherein one of the first plurality of memory cells is electrically connected to one of a plurality of bit lines, and
wherein the first circuit is configured to select any one of the plurality of bit lines and amplify and output a potential of the selected bit line.
In the similar field of endeavor of memory cells, Fig. 2 of Kajigaya discloses wherein one of the first plurality of memory cells (Fig. 2, plurality of memory cells MC, ¶ [0036]) is electrically connected to one of a plurality of bit lines (Fig. 2, local bit lines LBL, ¶ [0036]), and
wherein the first circuit (LSA) is configured to select any one of the plurality of bit lines (LBL) and amplify and output a potential of the selected bit line (“This structure enables the local sense amplifier LSA to sense and amplify the signal on a selected local bit line LBL”, ¶ [0043]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor device of Yokoyama with the first circuit as disclosed by Kajigaya, to allow selective reading of the memory cell array (see Kajigaya, ¶ [0042]).
Regarding claim 7, Yokoyama, Yamazaki and Kajigaya together disclose the semiconductor device according to claim 5 as applied above, but Yokoyama and Yamazaki fail to disclose wherein each of the first plurality of memory cells is electrically connected to a word line, and
wherein the first circuit is configured to amplify a signal supplied to the word line.
In the similar field of endeavor of memory cells, Fig. 2 of Kajigaya discloses wherein each of the first plurality of memory cells (MC) is electrically connected to a word line (WL), and
wherein the first circuit (LSA) is configured to amplify a signal supplied to the word line (WL) (“data of the memory cell MC corresponding to the selected word line WL is read out to the local bit line LBL, and is inputted to the local sense amplifier LSA”, ¶ [0049]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor device of Yokoyama with the first circuit as disclosed by Kajigaya, to allow selective reading of the memory cell array (see Kajigaya, ¶ [0042]).
Regarding claim 17, Yokoyama, Yamazaki and Kajigaya together disclose the semiconductor device according to claim 5 as applied above, and Fig. 13 of Yokoyama further discloses wherein the second substrate (10) is a silicon substrate (“The semiconductor layer 10S2 includes, for example, single-crystal silicon”, ¶ [0075]).
Regarding claim 18, Yokoyama, Yamazaki and Kajigaya together disclose the semiconductor device according to claim 5 as applied above, but Yokoyama and Kajigaya fail to disclose wherein the metal oxide comprises In, Ga and Zn.
In the similar field of endeavor of semiconductor storage devices, Fig. 5 of Yamazaki discloses wherein the metal oxide comprises In, Ga and Zn (“the oxide 704, a metal oxide such as an In-M-Zn oxide (M is one or more of…, gallium”, ¶ [0166]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor layer of Yokoyama with the metal oxide as disclosed by Yamazaki, to achieve more favorable on-state characteristics and higher mobility (see Yamazaki, ¶ [0165]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.A.N./ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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