DETAILED ACTION
This Office action responds to the application filed on 11/27/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2, 3, 4, 5, 8, 9, 10, 11, 12, 15, & 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "the terminal-section side of the chip mounting portion" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Additionally Claim 2 recites the limitation “each chip support body” in line 4, meaning more than one chip support body. Claim 1, on which Claim 2 depends, establishes “and a chip support body is provided between the plurality of chip-use terminals” in line 17. Claim 1 does not establish, i.e., a plurality of chip support bodies. Applicant’s specification states a plurality of chip support bodies Sa, Sb, & Sc, but the wording of the Claim 1 limitation claims a singular chip support body. Therefore, the limitation renders the claim indefinite.
Claim 3 recites the limitation "the terminal-section side of the chip support body" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 4 recites the limitation "the terminal-section side" in lines 6-7. There is insufficient antecedent basis for this limitation in the claim. Additionally, the limitation of Claim 4 is unclear as it does not clarify what element the terminal-section side pertains to or where the side is relative to.
Claim 4 recites the limitation "the display-area side" in line 5. There is insufficient antecedent basis for this limitation in the claim. Line 3 of Claim 4 recites “a display-area side of the chip-mounting portion” but it is unclear whether the former limitation is referencing the latter.
Regarding claim 4, the phrase " like" in the limitation “the chip support body is provided like double-sided comb teeth, but in a single piece,” renders the claim(s) indefinite because the claim(s) include(s) elements not actually disclosed (those encompassed by " like"), thereby rendering the scope of the claim(s) unascertainable. See MPEP § 2173.05(d). Claim 5 is rejected as being dependent on indefinite claim 4.
Claim 8 recites the limitation “a tip end of a portion outside the chip-mounting portion on which the chip support body is provided is alternately provided in a staggered pattern along the longer side of the chip-mounting portion” in lines 2-4. Applicant’s specification states a plurality of chip support bodies Sa, Sb, & Sc, but the wording of Claims 3, 2, & 1 claims a singular chip support body. It is unclear how a singular tip end would be alternately provided in a staggered pattern. Therefore, the limitation renders the claim indefinite.
Claim 9 recites the limitation “the chip-use terminal” in line 6. There is insufficient antecedent basis for this limitation in the claim. Line 13 of Claim 1, on which Claim 9 depends, recites “a plurality of chip-use terminals.” It is unclear whether it is intentional to describe limitations of a singular chip-use terminal or of the plurality of chip-use terminals.
Additionally, Claim 9 recites the limitation “and the organic insulating layer is thicker in a central portion in terms of a width direction than in both end portions in terms of the width direction” in lines 11-12.
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The current claim language does not clearly define central and both end portions to pertain to the organic insulating layer 19b. Even assuming the central and both end portions did pertain to organic insulating layer 19b, the comparisons of thickness would not be consistent with the claim language. It is unclear what the limitation intends to claim and the claim is indefinite. Claims 10 & 11 are rejected as being dependent on Claim 9.
Claim 10 recites the limitation "the flexible substrate layer side" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation "the terminal-section side" in lines 6-7. There is insufficient antecedent basis for this limitation in the claim. Additionally, the limitation of Claim 12 is unclear as it does not clarify what element the terminal-section side pertains to or where the side is relative to.
Claim 12 recites the limitation "the display-area side" in line 5. There is insufficient antecedent basis for this limitation in the claim. Line 3 of Claim 12 recites “a display-area side of the chip-mounting portion” but it is unclear whether the former limitation is referencing the latter.
Claim 15 recites the limitations “the chip support body provided between the plurality of third output terminals… the corresponding chip support body provided between the plurality of first output terminals… the corresponding chip support body provided between the plurality of second output terminals.” Claim 1, on which Claim 15 depends, establishes “and a chip support body is provided between the plurality of chip-use terminals” in line 17. Claim 1 does not establish, i.e., a plurality of chip support bodies. Applicant’s specification states a plurality of chip support bodies Sa, Sb, & Sc, but the wording of the Claim 1 limitation claims a singular chip support body. It is unclear whether Applicant wishes to claim a plurality of chip support bodies interconnected to other chip support bodies, or a singular chip support body interconnected to other portions of itself. The limitation renders the claim indefinite.
Claim 16 recites the limitation “each chip support body” in line 5, meaning more than one chip support body. Claim 1, on which Claim 16 depends, establishes “and a chip support body is provided between the plurality of chip-use terminals” in line 17. Claim 1 does not establish, i.e., a plurality of chip support bodies. Applicant’s specification states a plurality of chip support bodies Sa, Sb, & Sc, but the wording of the Claim 1 limitation claims a singular chip support body. Therefore, the limitation renders the claim indefinite.
Claims 4, 5, 8-11 are rejected solely under 35 U.S.C 112 until corrections are made. In order to further examination, interpretations of Claims 2, 3, 12, 15, & 16 are construed. The interpretations hereinafter are denoted by underlining and strikethrough as such: “a terminal-section side.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 12-18, & 20 are rejected under 35 U.S.C. 103 as being unpatentable over In (US 20200303468) in view of Yamashita (US 20090153765).
Regarding Claim 1, In (see, e.g., fig. 1, fig. 2, fig. 3b) shows a display device comprising:
a flexible substrate layer SUB (see, e.g., para.0060);
a thin film transistor layer DP-CL (see, e.g., para.0061, para.0069-0071) on the flexible substrate layer;
and a light-emitting element layer DP-OLED (see, e.g., para.0059) on the thin film transistor layer in such a manner as to correspond to a plurality of subpixels PX (see, e.g., para.0069) disposed in a display area DD-DA (see, e.g., para.0054),
the light-emitting element layer including a plurality of light-emitting elements (at least one organic light emitting diode, see, e.g., para.0062),
wherein a frame area DD-NDA (see, e.g., para.0054) is provided surrounding the display area,
a terminal section NDA-PD (see, e.g., para.0054) is provided extending in a single direction (horizontal) on an end portion of the frame area,
a chip-mounting portion NDA-TC (see, e.g., para.0079) is provided between the display area and the terminal section,
the chip-mounting portion being rectangular in a plan view and having a longer side extending in the direction (horizontal) in which the terminal section extends (see, e.g., fig. 3b),
a plurality of chip-use terminals TC-PD1 & TC-PD2 (see, e.g., para.0080) are provided in a single row on the chip-mounting portion,
and a plurality of terminal lines DL (see, e.g., para.0072) are provided extending parallel to each other in such a manner as to correspond to the plurality of chip-use terminals and being electrically connected respectively to the plurality of chip-use terminals,
In, however, fails to show
and a chip support body is provided between the plurality of chip-use terminals on the chip-mounting portion.
Yamashita (see, e.g., fig. 3, fig. 9, para.0070-0074), in a similar device to In, teaches that a chip support body 70 is provided between the plurality of chip-use terminals on the chip-mounting portion would effectively suppress the generation of excess leakage current.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the chip support body of Yamashita in the device of In to effectively suppress the generation of excess leakage current.
Regarding Claim 2, In (see, e.g., fig. 3b), in view of Yamashita (see, e.g., annotated figure 5), shows the display device according to claim 1,
wherein as the plurality of chip-use terminals ,
a plurality of input terminals TC-PD2 (input data from DP-PD, see, e.g., ) are provided in a single row along a longer side on a terminal-section side of the chip-mounting portion,
and the chip support body 70 is provided in an insular manner between the plurality of input terminals (see, e.g., annotated figure 5).
Regarding Claim 12, In, in view of Yamashita (see, e.g., annotated figure 5, para.0070), shows the display device according to claim 1,
wherein as the plurality of chip-use terminals,
a plurality of output terminals 14a (see, e.g., para.0070) are provided in a single row along a longer side on a display-area side of the chip-mounting portion,
the plurality of output terminals include:
a plurality of first output terminals (top row of 14a, see, e.g., annotated figure 5) provided in a single row on a display-area side;
a plurality of second output terminals (bottom row of 14a, see, e.g., annotated figure 5) provided in a single row on a terminal-section side;
and a plurality of third output terminals (middle row of 14, see, e.g., annotated figure 5) provided in a single row between the plurality of first output terminals and the plurality of second output terminals,
and the plurality of first output terminals, the plurality of third output terminals, and the plurality of second output terminals are repeatedly provided in an order of the plurality of first output terminals, the plurality of third output terminals, and the plurality of second output terminal along the longer side of the chip-mounting portion.
Regarding Claim 13, In, in view of Yamashita (see, e.g., annotated figure 5, fig. 5), shows the display device according to claim 12,
wherein the chip support body 70 is respectively provided between the plurality of first output terminals (top row of 14a) and between the plurality of second output terminals (bottom row of 14a).
Regarding Claim 14, In, in view of Yamashita (see, e.g., annotated figure 5, fig. 5), shows the display device according to claim 13,
wherein the chip support body 70 is not provided between the plurality of third output terminals (alternate of 14a, see, e.g., annotated figure 5).
Regarding Claim 15, In, in view of Yamashita (see, e.g., annotated figure 5, fig. 7), shows the display device according to claim 12,
wherein the chip support body 70 is respectively provided between the plurality of first output terminals (top row of 14a), between the plurality of second output terminals (bottom row of 14a), and between the plurality of third output terminals (middle row of 14a, see, e.g., annotated figure 5),
and the chip support body 70 provided between the plurality of third output terminals is respectively interconnected to the corresponding chip support body provided between the plurality of first output terminals and the corresponding chip support body provided between the plurality of second output terminals (embodiment of 70 chip support body is connected see, e.g., fig. 7).
Regarding Claim 16, In (see, e.g., fig. 3b), in view of Yamashita (see, e.g., annotated figure 7, para.0071) shows the display device according to claim 1,
wherein as the plurality of chip-use terminals, a plurality of shorter-side terminals (right side 14a) are provided in a single row along a shorter side of the chip-mounting portion on the chip-mounting portion (see, e.g., annotated figure 7),
and the support body is provided in an insular manner between the plurality of shorter-side terminals (insulating member and isolated terminals, see, e.g., para.0071).
Regarding Claim 17, In (see, e.g., figs 3a-b, para.0079), in view of Yamashita (see, e.g., fig. 9, para.0070), shows the display device according to claim 1,
wherein an integrated circuit chip TC of In (see, e.g., para.0079) or 50 of Yamashita (see, e.g., fig. 9) is mounted to the chip-mounting portion via an anisotropic conductive film 60 (see, e.g., para.0070).
Regarding Claim 18, In, in view of Yamashita (see, e.g., fig. 9, para.0070-0074), shows the display device according to claim 17,
wherein a plurality of bumps 51 (see, e.g., fig. 9, para.0070) are provided on a back face of the integrated circuit chip in such a manner as to correspond to the plurality of chip-use terminals TC-PD1 & TC-PD2 (corresponding to 14a of Yamashita, see, e.g., para.0071),
the anisotropic conductive film contains conductive particles 61 (see, e.g., para.0072),
and the plurality of bumps and the plurality of chip-use terminals are electrically respectively connected via the conductive particles.
Regarding Claim 20, In (see, e.g., fig. 2, para.0062), in view of Yamashita, shows the display device according to claim 1,
wherein each of the plurality of light-emitting elements is an organic electroluminescence element (OLED, see, e.g., para.0062).
Claims 3, 6, & 7 are rejected under 35 U.S.C. 103 as being unpatentable over In (US 20200303468) in view of Yamashita (US 20090153765) and further in view of Moh (US 20150187803).
Regarding Claim 3, In, in view of Yamashita, shows the display device according to claim 2,
In, in view of Yamashita, however, fails to show
wherein a terminal-section side of the chip support body provided with respect to the plurality of input terminals is disposed outside the chip-mounting portion M.
Moh (see, e.g., fig. 1, fig. 6, para.0049, para.0079, para.0096), in similar device to In, in view of Yamashita, shows a configuration wherein a terminal-section side A3 of the chip support body 112 provided with respect to the plurality of input terminals IP1-2 & IL1-2 is disposed outside the chip-mounting portion A1 (under chip 200) would be an obvious and suitable configuration for the chip support body of In, in view of Yamashita.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Moh, wherein the chip support body is disposed outside the chip-mounting portion, in the device In, in view of Yamashita, as an obvious and suitable configuration for the chip support body.
Regarding Claim 6, In, in view of Yamashita and further in view of Moh (see, e.g., annotated figure 1, para.0079-0082), shows the display device according to claim 3,
wherein a portion outside the chip-mounting portion A1 (under chip 200) on which the chip support body 112 (see, e.g., para.0082) is provided has a large width on a peripheral end of the chip-mounting portion (see, e.g., annotated figure 1).
Under broadest reasonable interpretation the limitation “a portion… on which the chip support body is provided has a large width” is interpreted as any element on which the chip support body is provided. Therefore the substrate 110 of Moh on which the chip support body is provide would have the large width.
Additionally, the limitation “a large width” is broad and does not limit the claim to any specific width parameter.
Regarding Claim 7, In, in view of Yamashita and further in view of Moh (see, e.g., annotated figure 1, para.0079-0082), shows the display device according to claim 3,
wherein a portion outside the chip-mounting portion A1 (under chip 200) on which the chip support body is provided is tapered toward a tip end (corner of 110, see, e.g., annotated figure 1).
Similar to Claim 6, the limitation “a portion… on which the chip support body is provided is tapered toward a tip end” is interpreted as any element on which the chip support body is provided. Applicant’s specification shows the chip support body Se (see, e.g., fig. 16, para.0098) tapered towards a tip end. However, the wording of the limitation defines the portion, on which the chip support body is provided, to be tapered towards a tip end. Thus, the portion of substrate 110 (see, e.g., annotated figure 1) tapering to a corner is sufficient to render the claim obvious.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over In (US 20200303468) in view of Yamashita (US 20090153765) and further in view of Ohara (US 20160043340).
Regarding Claim 19, In (see, e.g., fig. 2, para.0063), in view of Yamashita, shows the display device according to claim 1, further comprising
a sealing film TFE (see, e.g., para.0063)
In, in view of Yamashita, however, fails to show
the sealing film including a first inorganic sealing film, an organic sealing film, and a second inorganic sealing film, all of which are sequentially stacked, so as to cover the light-emitting element layer.
Ohara (see, e.g., fig. 1, fig. 4, fig. 5, para.0048), in a similar device to In, in view of Yamashita,, teaches that a sealing film sealing film including a first inorganic sealing film L1, an organic sealing film L2, and a second inorganic sealing film L3, all of which are sequentially stacked, so as to cover the light-emitting element layer would be an obvious and suitable configuration for the sealing film.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the sealing film of Ohara in the device of In, in view of Yamashita, as an obvious and suitable configuration for the sealing film.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/F.R.D./ Examiner, Art Unit 2814
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814