DETAILED ACTION 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. General Remarks 2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection. 3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs. 4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. Specification 5. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: “ Semi-Superjunction MOSFET Device and Manufacturing Method Thereof ” Appropriate correction is required. Claim Rejections - 35 USC § 102 6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 7. Claims 1, 3, 5-6 and 8-9 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Sundaresan, Siddarth et al. (Pub No. US 20220384565 A1) (hereinafter, Sundaresan). Sundaresan, Fig 1a: MOSFET Device with Shield, Source and P-well regions Re Claim 1, (Original) Sundaresan teaches a manufacturing method for a metal oxide semiconductor field effect transistor (MOSFET) device (MOSFET; Fig 1a), comprising: providing a substrate (SiC substrate/Drift layer; 202/204; Fig 2a; ¶[0168]), forming a patterned mask layer (1st Hard Mask; 206; Fig 2a; ¶[0168]) on the substrate, (See Fig 2a below) Sundaresan, Fig 2a: Masking layer disposed over substrate/drift layer preceding ion implantation step and implanting first ions of a first conductivity type (Implanting p-type ions; Fig 2b; ¶[0171]) into a surface layer (Surface of drift layer; Fig 2b) of the substrate by using the patterned mask layer as a mask (Ion implantation performed through hard mask 206 to form well region 208; Fig 2b; ¶[0171]), to form a well region (Well region; 208; Fig 2b; ¶[0171]); (See Fig 2b below) Sundaresan, Fig 2b: Forming well region around masking layer forming spacers (Spacers; Fig 2d; ¶[0173]) on both sidewalls of the patterned mask layer, (See Fig 2d below) Sundaresan, Fig 2d: Forming spacers around masking layer and implanting ions of a second conductivity type (N-type; ¶[0181]) into a surface layer (Surface of well region 208; Fig 2h) of the well region by using the patterned mask layer and the spacers as a mask (Mask with spacers is used to form source region 214; ¶[0180-0181]), to form a source region (Source region; 214; Fig 2h; ¶[0181]); (See Fig 2h below) Sundaresan, Fig 2h: Implanting ions to form source region implanting second ions (P+ ions are implanted; ¶[0179]) of the first conductivity type into the substrate below the well region by using the patterned mask layer and the spacers as a mask (Mask with spacers is used to form shield region 212 below p-well 208; Figs 2f/2h; ¶[0179]), wherein the second ions are easier to diffuse in the substrate than the first ions (Per ¶¶[0172,0185] second ions are annealed with higher temperature which are easier to diffuse than first ions) to form a semi-superjunction (Shield region; 212; Fig 2h; ¶[0179]) connected to a bottom of the well region and self-aligned (Shield region 212 is aligned under source region 214; Fig 2h) with the source region; and forming, on the substrate, a gate oxide layer (Gate oxide (not shown); Fig s 1a/ 2j; ¶[0186]) and a gate (Gate metal/polysilicon; 218; Fig s 1a/ 2j; ¶[0187]) that are sequentially stacked, wherein a region in which the well region overlaps the gate is used as a channel (MOSFET channel; ¶[0181]) of the MOSFET device. Re Claim 3, (Original) Sundaresan teaches the manufacturing method according to claim 1, wherein after the second ions of the first conductivity type (P+ ions are implanted; ¶[0179]) are implanted into the substrate (SiC substrate/Drift layer; 202/204; Fig 2a; ¶[0168]) below the well region (Well region; 208; Fig 2b; ¶[0171]), annealing activation is performed (Annealing is performed after ion-implantation steps; ¶[0185]). and during the annealing activation, the second ions are easier to diffuse (Per ¶¶[0172,0185] second ions are annealed with higher temperature which are easier to diffuse than first ions) in the substrate than the first ions, and then, the second ions form the semi-superjunction (Shield region; 212; Fig 2h; ¶[0179]) after being diffused in the substrate. Re Claim 5, (Original) Sundaresan teaches the manufacturing method according to claim 3, wherein the first ions (P-type ions; Fig 2b; ¶[0171]) comprise aluminum ions (Ions for well region 208 comprise of Aluminum; ¶[0171]), and the second ions (P+ ions; ¶[0179]) comprise boron ions and/or boron fluoride ions (Ions for shield region 212 comprise of Boron ¶[0179]). Re Claim 6, (Original) Sundaresan teaches the manufacturing method according to claim 5, wherein implantation process parameters of the first ions (P-type ions; Fig 2b; ¶[0171]) comprise implantation energy ranging from 50 keV to 800 keV (Implantation energy ranging from 10 kiloelectron volts (keV) to 10 mega electron volts (MeV); ¶[0171]) and an implantation dose ranging from 1E12/cm2 to 9E13/cm2 (1E12/cm2 to 1E15/cm2; ¶[0171]); and/or implantation process parameters of the second ions comprise implantation energy ranging from 100 keV to 2 MeV (Implantation energy ranging from 100 kiloelectron volts (keV) and 5 mega electron volts (MeV); ¶[0179]) and an implantation dose ranging from 1 E12/cm2 to 5E 14/cm2 (Shield region implantation dose is that first ions, i.e. 1E12/cm2 to 1E15/cm2; ¶[0179]). Re Claim 8, (Currently Amended) Sundaresan teaches the manufacturing method according to any one of claim 1, further comprising: forming an interlayer dielectric layer (ILD; 220; Fig 2j; ¶[0187]) on the substrate (SiC substrate/Drift layer; 202/204; Fig 2a; ¶[0168]), wherein the interlayer dielectric layer buries the gate (Gate metal/polysilicon; 218; Fig 2j; ¶[0187]) and exposes a part (Outer portions of source region 214; Fig 2j) of the source region (Source region; 214; Fig 2h; ¶[0181]); forming a source metal layer (Pad metal above ILD; 224; Fig 2j; ¶[0187]) on the interlayer dielectric layer, wherein the source metal layer is electrically connected (Through silicide layer 222 above source region 214; Fig 2j) to the source region; and forming a drain metal layer (Pad metal below substrate 202; 224; Fig 2j; ¶[0187]) on a bottom surface (Bottom surface of substrate 202; Fig 2j) of the substrate. Re Claim 9, (Original) Sundaresan teaches a metal oxide semiconductor field effect transistor (MOSFET) device (MOSFET; Fig 1a), comprising: a substrate (SiC substrate/Drift layer; 202/204; Fig 2a; ¶[0168]), wherein a well region (Well region; 208; Fig 2b; ¶[0171]) and a semi-superjunction (Shield region; 212; Fig 2h; ¶[0179]) that are of a first conductivity type (P-type ions; Fig 2b; ¶[0171]) and a source region (Source region; 214; Fig 2h; ¶[0181]) of a second conductivity type (N-type; ¶[0181]) are formed in the substrate, the well region is formed in a surface layer (Surface of drift layer 204; Fig 2b) of a partial region (Regions in drift layer 204 on sides of 1st hard mask 206; Fig 2b) of the substrate, the source region is formed in a surface layer (Upper surface of well region 208; Fig 2j) of the well region, and the semi-superjunction is formed in the substrate below (Shield region 212 is formed below well region 208; Fig 2j) the well region, is self-aligned (Shield region 212 is aligned underneath source region 214; Fig 2j) with the source region, and is connected to a bottom (Shield region 212 contacts bottom of well region 208; Fig 2j) of the well region; and a gate oxide layer (Gate oxide (not shown); Fig 2j; ¶[0186]) and a gate (Gate metal/polysilicon; 218; Fig 2j; ¶[0187]), sequentially stacked on the substrate, wherein the gate overlaps (Gate metal 218 overlaps source region 214 and well region 208; Fig 2j) the source region, and the well region on a side (Well region 208 extends to side of source region 214; Fig 2j) of the source region and located at a bottom (Bottom of gate metal 218; Fig 2j) of the gate forms a channel (MOSFET channel; ¶[0181]) of the MOSFET device. Claim Rejections - 35 USC § 103 8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 9. Claims 2, 4, 7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Sundaresan, Siddarth et al. (Pub No. US 20220384565 A1) (hereinafter, Sundaresan) as applied to claim s 1 and 9 above, and further in view of Tang, Xiao-Yan et al. (Pub No. CN 102832248 A) (hereinafter, Tang). Re Claim 2, (Original) Sundaresan teaches the manufacturing method according to claim 1, wherein the provided substrate comprises a base (N+ substrate; 202; Fig 2j; ¶[0168]) of the second conductivity type (N-type; ¶[0181]) and a drift layer (Drift layer; 204; Fig 2j; ¶[0168]) of the second conductivity type, wherein the drift layer is a silicon carbide layer (SiC substrate comprises of the drift layer; ¶[0008]), and the well region (Well region; 208; Fig 2b; ¶[0171]) and the semi-superjunction (Shield region; 212; Fig 2h; ¶[0179]) are both formed in the drift layer. However, Sundaresan does not teach a buffer layer of the second conductivity type In the same field of endeavor, Tang teaches a buffer layer (Current-expansion layer; 10; Fig 2; ¶[0056]) of the second conductivity type (N-type; ¶[0056]) . (See Fig 2 below) Tang, Fig 2: MOSFET Device with buffer layer of second conductivity type Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined a buffer layer of the second conductivity type, as disclosed by Tang, with the semiconductor structure as taught by Sundaresan. One would have been motivated to do this with a reasonable expectation of success because the buffer layer reduces further on-resistance by stopping the electric field from reaching the substrate below, preventing breakdown. Re Claim 4, (Original) Sundaresan teaches the manufacturing method according to claim 3, wherein after the second ions are implanted (P+ ions are implanted; ¶[0179]), and before the annealing activation is performed to form the semi-superjunction (Shield region; 212; Fig 2h; ¶[0179]), the manufacturing method further comprises: removing (Removing composite hard mask stack; ¶[0188]) the patterned mask layer (1st Hard Mask; 206; Fig 2a; ¶[0168]) and the spacers (Spacers; Fig 2d; ¶[0173]) . However, Sundaresan does not teach forming a body contact region of the first conductivity type and a junction implantation region of the second conductivity type through implantation of corresponding ions, wherein the body contact region is formed in the source region and extends into a part of the well region to short-circuit the source region and the well region, and the junction implantation region is located at a bottom of the gate and between parts of the well region on both sides of the gate. In the same field of endeavor, Tang teaches forming a body contact region (Ohmic contact region; 5; Fig 2; ¶[0035]) of the first conductivity type (P-type; ¶[0035]) and a junction implantation region (JFET region; 7; Fig 2; ¶[0035]) of the second conductivity type (Per ¶[0018] nitrogen ions implanted into SiC are an N-type dopant) through implantation of corresponding ions, wherein the body contact region is formed in the source region (Ohmic contact region 5 is formed in edge of source region 4; ¶[0019]) and extends into a part of the well region (P well; 6; Fig 2; ¶[0006]) to short-circuit (Ohmic contact provides a low-resistance path for current, i.e. short circuiting source and well region) the source region and the well region, and the junction implantation region is located at a bottom (Bottom of gate 2; Fig 2) of the gate (Gate; 2; Fig 2; ¶[0006]) and between parts (Between inner sides of well region 6; Fig 2) of the well region on both sides of the gate. Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined a body contact region of the first conductivity type and a junction implantation region of the second conductivity type through implantation of corresponding ions, wherein the body contact region is formed in the source region and extends into a part of the well region to short-circuit the source region and the well region, and the junction implantation region is located at a bottom of the gate and between parts of the well region on both sides of the gate, as disclosed by Tang, with the semiconductor structure as taught by Sundaresan. One would have been motivated to do this with a reasonable expectation of success because the JFET region act as a variable resistance controlled by the gate voltage, and is juxtaposed next to the body contact region such that the resistance which is lowered by the short-circuit effect between the well and source region may be adjusted accordingly. Re Claim 7, (Original) Sundaresan teaches the manufacturing method according to claim 5, wherein process conditions of the annealing activation (High-temperature annealing ; ¶[0185]) comprise an annealing temperature ranging 1500°C to 1900°C (1600 - 2000 °C; ¶[0185]). However, Sundaresan does not teach an annealing time ranging from 2 min to 200 min. In the same field of endeavor, Tang teaches an annealing time (Annealing time; ¶[0027]) ranging from 2 min to 200 min (10 minutes; ¶[0027]). Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined an annealing time ranging from 2 min to 200 min, as disclosed by Tang, with the annealing activation process conditions as taught by Sundaresan. One would have been motivated to do this with a reasonable expectation of success because Shorter, high-temperature cycles prevent excessive dopant movement, which is critical for maintaining precise junction depths in scaled devices. Re Claim 10, (Original) Sundaresan teaches the MOSFET device according to claim 9, comprising a base (N+ substrate; 202; Fig 2j; ¶[0168]) of the second conductivity type (N-type; ¶[0181]) and a drift layer (Drift layer; 204; Fig 2j; ¶[0168]) of the second conductivity type, wherein the drift layer is a silicon carbide layer (SiC substrate comprises of the drift layer; ¶[0008]), and the well region (Well region; 208; Fig 2b; ¶[0171]) and the semi-superjunction (Shield region; 212; Fig 2h; ¶[0179]) are both formed in the drift layer; and ions of the first conductivity type (P-type ions; Fig 2b; ¶[0171]) doped in the well region (Well region; 208; Fig 2b; ¶[0171]) comprise aluminum ions (Ions for well region 208 comprise of Aluminum; ¶[0171]), and ions of the first conductivity type (P+ ions; ¶[0179]) doped in the semi-superjunction (Shield region; 212; Fig 2h; ¶[0179]) comprise boron ions and/or boron fluoride ions (Ions for shield region 212 comprise of Boron ¶[0179]). However, Sundaresan does not teach a buffer layer of the second conductivity type In the same field of endeavor, Tang teaches a buffer layer (Current-expansion layer; 10; Fig 2; ¶[0056]) of the second conductivity type (N-type; ¶[0056]) . Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined a buffer layer of the second conductivity type, as disclosed by Tang, with the semiconductor structure as taught by Sundaresan. One would have been motivated to do this with a reasonable expectation of success because the buffer layer reduces further on-resistance by stopping the electric field from reaching the substrate below, preventing breakdown. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. [1] Jiang, Chang-fu et al. (Pub No. CN115117145B) discloses The invention claims a SiC-based MOSFET device with low on-resistance and a preparation method thereof, wherein the drift layer comprises an nx first drift layer and an n-second drift layer arranged on the nx first drift layer; The SiC-based MOSFET device with segmented doped epitaxial structure of the invention uses the high-doped drift layer far away from the main junction region to reduce the series resistance of the device, and uses the low-doped layer of the main junction region to improve the protection effect of the p-type shielding layer, reducing the Miller charge of the device, so as to improve the switching capability of the SiC based MOSFET device. [2] Oritsuki Yasunori et al. (Pub No. DE102014201521A1 ) a MOSFET device with a drift layer, source/drain electrode, and regions of p-type and n-type conductivities disposed beneath a gate metal. an object of the invention to provide a semiconductor device which prevents a parasitic bipolar operation from being performed by a surge current flowing to a source region, thereby preventing a device from being damaged. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT TIMOTHY EDWARD DUREN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (703)756-1426 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT 07:30 - 17:00 PST . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. 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