Prosecution Insights
Last updated: April 19, 2026
Application No. 18/562,502

SUBSTRATE PROCESSING METHOD

Non-Final OA §103
Filed
Nov 20, 2023
Examiner
YAP, DOUGLAS ANTHONY
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Tokyo Electron Limited
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
3y 3m
To Grant
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
43 granted / 49 resolved
+19.8% vs TC avg
Moderate +12% lift
Without
With
+12.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
48 currently pending
Career history
97
Total Applications
across all art units

Statute-Specific Performance

§103
50.9%
+10.9% vs TC avg
§102
25.2%
-14.8% vs TC avg
§112
21.2%
-18.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 49 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claims 1, and by extension dependent claims 2-12 are objected to because of the following informalities: (1) the claim may need to reword “laser light,” found in the limitation of “a first absorption layer configured to absorb laser light,” to “a laser light” to satisfy antecedence basis formalities. (2) the limitations of “irradiating the laser light with respect to the first substrate from a side opposite to the second substrate” and “irradiating the laser light transmitted through the first substrate on the first absorption layer, to form a modified layer in the first absorption layer” both recite the same phrase “irradiating the laser light,” could be interpretated that the laser irradiation is done twice to the substrate. The instant application discloses irradiating the laser light only once for each embodiment. Claims 2, 3, 6, and 8 are objected to because of the following informalities: these claims may need to reword “detection light” to “a detection light” to satisfy antecedence basis formalities. Appropriate correction is required. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1 and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Shimoda (JP H10125929 A; see English translation in FOR mailed on 20 November 2023) in view of Sreenivasan (US 2021/0134640 A1) and Noda (US 2005/0233547 A1) as evidenced by Hamasha (NPL: Photoacoustic Measurements of black carbon light absorption coefficients in Irbid city, Jordan) and Yamaguchi (US 2022/0340700 A1). Regarding claim 1, Shimoda teaches a substrate processing method comprising: preparing a laminated substrate (see Overview) including a first substrate (1), a first absorption layer (21; Figs. 5 & 6 show 21 absorbing laser light 7) configured to absorb laser light (7), a reflective layer (22), and a second substrate (4) in this order; irradiating the laser light with respect to the first substrate from a side opposite to the second substrate (see Fig. 5); irradiating the laser light transmitted through the first substrate on the first absorption layer, to form a modified layer (¶ [0110]-[0111]: 7 causes a phase change in 21 due to ablation) in the first absorption layer; and separating the first substrate and the second substrate using the modified layer as a starting point (see Fig. 6). Shimoda further teaches the second substrate to have a transistor (¶ [0014], [0085]-[0086]: transfer layer 4 is a thin film transistor). However, Shimoda does not teach the method wherein a device layer is between the reflective layer and the second substrate. Sreenivasan, in the same field of invention, teaches a substrate processing method (see Fig. 16C) comprising a first absorption layer (902, see Figs. 16B and 16C; ¶ [0109]: “the carrier wafer is de-bonded by removing adhesive 902 using laser radiation 1603” ), a device layer (transistor 206; not labelled in Fig. 16 but shown in Fig. 2), and a second substrate (201/203, see Figs. 2 & 16B, which shows 206 above 201/203), wherein the device layer is above the first absorption layer and below the second substrate (203; Fig. 16B, when viewed upside down, shows 206, which is not labelled, to be above 902 and below 203). Hence, Shimoda in view of Sreenivasan teaches a device layer in between the reflective layer (Sreenivasan’s 902 is analogous to both first absorption layer and reflective layer) and the second substrate. A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Sreenivasan into the method of Shimoda to insert a device layer in between the reflective layer and the second substrate. The ordinary artisan would have been motivated to modify Shimoda in the manner set forth above for at least the purpose of fabricating transistors (¶ [0060]: 206 are transistors ) using known design methods and structures in the art, i.e., a transistor layer is patterned above a wafer (201) using lithography and etching methods (Sreenivasan Fig. 3) and for the further purpose of adding front-end high-resolution device layers in a “feedstock” design (202) to reduce cost (¶ [0060]). Shimoda further teaches the first absorption layer to be made of resin (¶ [0065]) and having a considerably small absorption coefficient with respect to laser light (¶ [0124]: light 7 can be radiated through 21 without loss) and the reflective layer is used to block the laser from reaching the second substrate (¶ [0123]). However, Shimoda in view of Sreenivasan does not teach the reflective layer to be a second absorption layer having an absorption coefficient with respect to the laser light higher than an absorption coefficient of the first absorption layer. Noda, in the same field of invention, teaches a light absorbing layer (¶ [0039]: carbon black) that allows the laser to pass through the first substrate (transparent support) and the first absorption layer (matrix-resin layer) and blocks the laser from reaching underlying structure in order to separate the underlying structure from the support (¶ [0039]). Hence, Noda teaches a second absorption layer (carbon black) having an absorption coefficient (as evidenced by Hamasha, see Abstract: 40.4 Mm-1 to 61.2 Mm-1, measured at 870 nm) with respect to the laser light (Noda ¶ [0032]: using laser at wavelengths of 350 nm to 2000 nm) higher than an absorption coefficient (as evidenced by Yamaguchi, see ¶ [0027]: 0.02 μm-1or less at 300 nm to 800 nm light wavelengths) of the first absorption layer (resin). A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to substitute the reflective layer of Shimoda with a second absorption layer that has an higher absorption coefficient, with respect to the laser light, than that of the first absorption layer, for the predictable result of blocking lasers from underlying structures while converting the trapped laser energy into heat that results in gas or voids in the first absorption layer, i.e., matrix-resin layer, which then results in the separation of the support wafer from the underlying structure (Noda ¶ [0039]) and for the further purpose of minimizing any damage to the structure during the separation process (¶ [0039] ). Regarding claim 10, the substrate processing method as claimed in claim 1, further comprising: bonding (Sreenivasan Fig. 9A, ¶ [0091]) a plurality of chips (there are multiple 202s on 901) including the device layer and the second substrate (each 202 consists of a 201/203 and a 206) to the first substrate (901) at intervals, wherein the plurality of chips and the first substrate are separated from one another by separating the first substrate and the second substrate from each other using the modified layer as a starting point (see Sreenivasan Fig. 16C-16D). Regarding claim 11, the substrate processing method as claimed in claim 1, further comprising: bonding (Sreenivasan Fig. 9A, ¶ [0091]) the second substrate (labelled as 203) having the device layer formed thereon to the first substrate (901) having a size (horizontal length of 901) identical to a size (horizontal length of 203) of the second substrate (Fig. 9A shows 203 having the same horizontal length as 901), wherein the device layer formed on the second substrate and the first substrate are separated from each other by separating the first substrate and the second substrate from each other using the modified layer as a starting point (see Sreenivasan Fig. 16C-16D). Regarding claim 12, Shimoda in view of Sreenivasan teaches the substrate processing method as claimed in claim 1,wherein the laser light has a wavelength of 3 nm to 350 nm Shimoda ¶ [0116]) and further teaches changing the wavelength to 350 nm to 1200 nm to impart a separating characteristic to the modified layer through the means of a phase change (Shimoda ¶ [0117]). Hence, a person of ordinary skill, prior to the effective date of the claimed invention, will find in obvious to optimize the range of the laser light wavelength from 8800 nm to 11000 nm depending on how the materials used in the first substrate, first absorption layer, or second absorption layer are affected by the laser at specific wavelengths. See also MPEP § 2144.05 (II)(A). Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Shimoda (JP H10125929 A; see English translation in FOR mailed on 20 November 2023) in view of Sreenivasan (US 2021/0134640 A1) and Noda (US 2005/0233547 A1) as applied to claim 1 above, and further in view of Yamauchi (WO 2012/133760 A1; see NPL for English translation ) and Budd (US 2019/0088481 A1). Regarding claim 2, Shimoda et al teach the substrate processing method as claimed in claim 1, but does not teach: wherein the laminated substrate includes an alignment mark, and further comprising: irradiating detection light that is used to detect the alignment mark in a direction identical to a direction of the laser light with respect to the alignment mark. Yamauchi, in the same field of invention, teaches a substrate processing method wherein the laminated substrate (53 & WT1 & RS1 & CP1; see Fig. 17; ¶ [0057]: these layers may be laminated) includes an alignment mark (MW2), and further comprising: irradiating detection light (55a; ¶ [0089]: 55a emits infrared light) that is used to detect the alignment mark in a direction (55a emits light upwards along the z-axis) opposite to a direction (downwards along the z-axis; Yamauchi teaches using laser to detach WT1 from chips CP1, see “debonding process” in Fig. 19 and ¶ [0186]; Shimoda et al in view of Yamauchi teaches the laser to be emitted from the top of substrate 53) of the laser light with respect to the alignment mark. A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Yamauchi into the method of Shimoda et a to add an alignment mark and to irradiate detection light, used to detect the alignment mark, in a direction opposite the direction of the laser light with respect to the alignment mark. The ordinary artisan would have been motivated to modify Shimoda et al in the manner set forth above for at least the purpose of ensuring proper alignment of the laminated wafer with respect to another substrate (51, see Yamauchi Fig. 17; ¶ [0054]) for the further purpose of reducing the processing time of transferring a plurality of chips to be vertically stacked on a substrate (¶ [0005]-[0007]; see Fig. 26). However, Shimoda et al. do not teach: irradiating detection light that is used to detect the alignment mark in a direction identical to a direction of the laser light with respect to the alignment mark. Budd, in the same field of invention, teaches a substrate processing method (Fig. 8B) comprising of irradiating detection light that is used to detect the alignment mark (26A) in a direction (fiducials 26A are seen by the vision system in an upwards direction) identical to a direction (laser lights are irradiating the substrate 26 in an upwards direction) of the laser light (39) with respect to the alignment mark. A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Budd into the method of Shimoda et al to change the direction of the infrared detection light from an opposite direction of the laser light to an identical direction of the laser light. The ordinary artisan would have noted that the Budd’s substrate (26: ¶ [0047]: made of silicon or glass) and Shimoda’s substrate (Shimoda ¶ [0044]: glass) allows both infrared and laser light to pass through. Hence, the position of the alignment mark can be changed to suit the preference of the ordinary skilled artisan. See also MPEP § 2144.04 (VI)(C). Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Shimoda (JP H10125929 A; see English translation in FOR mailed on 20 November 2023) in view of Sreenivasan (US 2021/0134640 A1) and Noda (US 2005/0233547 A1) as applied to claim 1 above, and further in view of Yamauchi (WO 2012/133760 A1; see NPL for English translation ). Regarding claim 3, Shimoda et al teach the substrate processing method as claimed in claim 1, but does not teach: wherein the laminated substrate includes an alignment mark, and further comprising: irradiating detection light that is used to detect the alignment mark in a direction opposite to a direction of the laser light with respect to the alignment mark. Yamauchi, in the same field of invention, teaches a substrate processing method wherein the laminated substrate (53 & WT1 & RS1 & CP1; see Fig. 17; ¶ [0014]) includes an alignment mark (MW2), and further comprising: irradiating detection light (55a; ¶ [0089] 55a emits infrared light) that is used to detect the alignment mark in a direction (55a emits light upwards along the z-axis) opposite to a direction (downwards along the z-axis; Yamauchi teaches using laser to detach WT1 from chips CP1, see “debonding process” in Fig. 19 and ¶ [0186]; Shimoda et al in view of Yamauchi teaches the laser to be emitted from the top of substrate 53) of the laser light with respect to the alignment mark. A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Yamauchi into the method of Shimoda et al. to add an alignment mark and to irradiate detection light, used to detect the alignment mark, in a direction opposite the direction of the laser light with respect to the alignment mark. The ordinary artisan would have been motivated to modify Shimoda et al. in the manner set forth above for at least the purpose of ensuring proper alignment of the laminated wafer with respect to another substrate (51, see Yamauchi Fig. 17; ¶ [0054]) for the further purpose of reducing the processing time of transferring a plurality of chips to be vertically stacked on a substrate (¶ [0005]-[0007]; see Fig. 26). Regarding claim 4, Shimoda et al. teach the substrate processing method as claimed in claim 1, and further teach the first absorption layer to be made of resin (Shimoda ¶ [0065]). However, Shimoda et al. do not teach: wherein the laminated substrate includes an alignment mark, and the alignment mark is disposed between the first substrate and the first absorption layer. Yamauchi in the same field of invention, teaches a substrate processing method wherein the laminated substrate (53 & WT1 & RS1 & CP1; see Fig. 17; ¶ [0014]) includes an alignment mark (MW2), and the alignment mark is disposed between the first substrate (WT1) and the first absorption layer (RS1, which is made of resin; labelled in Fig. 19). A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Yamauchi into the method of Shimoda et al. to add an alignment mark that is disposed between the first substrate and the first absorption layer. The ordinary artisan would have been motivated to modify Shimoda et al. in the manner set forth above for at least the purpose of ensuring proper alignment of the laminated wafer with respect to another substrate (51, see Yamauchi Fig. 17), by using the alignment mark with another alignment mark (MW1 on 51, see ¶ [0054]) for the further purpose of reducing the processing time of transferring a plurality of chips to be vertically stacked on a substrate (¶ [0005]-[0007]; see Fig. 26). Regarding claim 5, Shimoda et al teach the substrate processing method as claimed in claim 1, but does not teach wherein the laminated substrate includes an alignment mark, and the alignment mark is disposed between the first substrate and the first absorption layer. Yamauchi in the same field of invention, teaches a substrate processing method wherein the laminated substrate (53 & WT1 & RS1 & CP1; see Fig. 17; ¶ [0014]) includes an alignment mark (MW2), and the alignment mark is disposed between the first substrate (WT1) and the first absorption layer (RS1, which is made of resin; labelled in Fig. 19). A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Yamauchi into the method of Shimoda et al to add an alignment mark that is disposed between the first substrate and the first absorption layer. The ordinary artisan would have been motivated to modify Shimoda et al in the manner set forth above for at least the purpose of ensuring proper alignment of the laminated wafer with respect to another substrate (51, see Yamauchi Fig. 17), by using the alignment mark with another alignment mark (MW1 on 51, see ¶ [0054]) for the further purpose of reducing the processing time of transferring a plurality of chips to be vertically stacked on a substrate (¶ [0005]-[0007]; see Fig. 26). Although Yamauchi does not teach the alignment mark is disposed between the second absorption layer and the device layer, Yamauchi further teaches the alignment mark is being detected through infrared light and that infrared light penetrates the first absorption layer (¶ [0088]: infrared passes through resin layer RS). Hence, an ordinary artisan will find it obvious to try in placing the alignment mark either between the first substrate and the first absorption layer or between the second absorption layer and the device layer. Since the infrared light comes from below, then a position that is between the second absorption layer and the device layer would be reached by the infrared light first compared to the position between the first substrate and the first absorption layer. See also MPEP § 2144.02: reliance on logic and scientific principles. Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Shimoda (JP H10125929 A; see English translation in FOR mailed on 20 November 2023) in view of Sreenivasan (US 2021/0134640 A1) and Noda (US 2005/0233547 A1), as applied to claim 1 above, in further view of Yamauchi (WO 2012/133760 A1; see NPL for English translation ) and Mu (US 2020/0057183 A1). Regarding claim 6, Shimoda et al teach the substrate processing method as claimed in claim 1, and further teach the second absorption layer absorbs the laser light (Noda ¶ [0039]), but does not teach the laminated substrate includes an alignment mark, with the method further comprising of a detection light used to detect the alignment mark. Yamauchi, in the same field of invention, teaches a substrate processing method wherein the laminated substrate (53 & WT1 & RS1 & CP1; see Fig. 17; ¶ [0014]) includes an alignment mark (MW2), with the method further comprising of a detection light (¶ [0089]: 55a emits infrared light) used to detect the alignment mark. A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Yamauchi into the method of Shimoda et al to add an alignment mark to the laminated substrate and to use a detection light to detect the alignment mark. The ordinary artisan would have been motivated to modify Shimoda et at in the manner set forth above for at least the purpose of ensuring proper alignment of the laminated wafer with respect to another substrate (51, see Yamauchi Fig. 17), by using the alignment mark with another alignment mark (MW1 on 51, see ¶ [0054]) for the further purpose of reducing the processing time of transferring a plurality of chips to be vertically stacked on a substrate (¶ [0005]-[0007]; see Fig. 26). Shimoda et al. further teach the second absorption layer to be a multilayered film (Shimoda ¶ [0054]: 22 can have a plurality of layers), with the laser light to have a wavelength of ranging from 3nm to 350 nm (Shimoda ¶ [0116]]). However, Shimoda et al. does not teach the second absorption layer transmits the detection light. Mu, in the same field of invention, teaches a multilayer film (11) that transmit infrared light (¶ [0005]). Hence, Shimoda et al in view of Mu teaches the second absorption layer transmit detection light. A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Mu into the method of Shimoda et al to have the second absorption layer transmit infrared detection light. The ordinary artisan would have been motivated to modify Shimoda et al in the manner set forth above for at least the purpose of using the multilayered film as band pass filter that would allow the detection light (infrared, known in the art to have wavelengths ranging from 780 nm to 1 mm) to pass through (Mu ¶ [0004]), thus ensuring the alignment marks of as taught by Yamauchi can be detected, but would block and/or absorb the laser light (Fig. 3 shows the filter allow wavelengths of 920nm - 960 nm), thus protecting the device layer of Sreenivasan from the laser. Regarding claim 7, the second absorption layer includes a high refractive index layer (111; see Mu Fig. 1) and a low refractive index layer (112) that are arranged alternately and repeatedly (see ¶ [0038] and Fig. 1). Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Shimoda (JP H10125929 A; see English translation in FOR mailed on 20 November 2023) in view of Sreenivasan (US 2021/0134640 A1) and Noda (US 2005/0233547 A1) as applied to claim 1 above, and further in view of Yamauchi (WO 2012/133760 A1; see NPL for English translation ) as evidenced by Burberry (US 2005/0259300 A1). Regarding claim 8, Shimoda et al teaches the substrate processing method as claimed in claim 1 and further teaches the second absorption layer absorbs the laser light (Noda ¶ [0039]), but Shimoda et al does not teach wherein the laminated substrate includes an alignment mark. Yamauchi, in the same field of invention, teaches a teaches a substrate processing method wherein the laminated substrate (53 & WT1 & RS1 & CP1; see Fig. 17; ¶ [0014]) includes an alignment mark (MW2 and/or MC1, see Fig. 17 and 12). A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Yamauchi into the method of Shimoda et al to add an alignment mark to the laminated substrate. The ordinary artisan would have been motivated to modify Shimoda et at in the manner set forth above for at least the purpose of ensuring proper alignment of the laminated wafer with respect to another substrate (51, see Yamauchi Fig. 17), by using the alignment mark with another alignment mark (MW1 on 51, see ¶ [0054]) for the further purpose of reducing the processing time of transferring a plurality of chips to be vertically stacked on a substrate (¶ [0005]-[0007]; see Fig. 26). Shimoda et al further teach the method wherein the detection light is infrared (Yamauchi ¶ [0088]) and the second absorption layer (Noda ¶ [0039]: carbon black) absorbs detection light that is used to detect the alignment mark (as evidenced by Burberry ¶ [0023]: black layer absorbs infrared radiation). Regarding claim 9, the substrate processing method as claimed in claim 8, wherein the second absorption layer includes a black absorber (Noda ¶ [0039]: carbon black). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DOUGLAS YAP/Assistant Examiner, Art Unit 2899 /JOHN M PARKER/Examiner, Art Unit 2899
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Prosecution Timeline

Nov 20, 2023
Application Filed
Mar 11, 2026
Non-Final Rejection — §103 (current)

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Expected OA Rounds
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Grant Probability
99%
With Interview (+12.2%)
3y 3m
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