DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Cross-Reference to Related Applications
2. This application is a 371 of PCT/JP2021/026326 07/13/2021.
Preliminary amendment
3. Preliminary amendment filed on 11/28/2023 has been acknowledged and considered.
In the Preliminary amendment, the applicants have been amended the abstract, the specification and claims 3-5 and claims 7-9 and remained claims 1-2, 6 and 10-11.
Claims 1-11 are currently pending in the application.
Oath/Declaration
4. The oath/declaration filed on 11/28/2023 is acceptable.
Information Disclosure Statement
5. The office acknowledges receipt of the following items from the applicant:
Information Disclosure Statement (IDS) filed on 11/28/2023.
Specification
6. The specification is objected to for the following reason: The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed (see MPEP 606.01).
Claim Rejections-35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
7. Claims 1-11 are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
In claim 1, lines 21-22, a feature of “a third terminal electrode and a fourth terminal electrode provided to the second gate electrode across from the resin substrate” should be read as “a third terminal electrode and a fourth terminal electrode provided to the second semiconductor layer across from the resin substrate”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless --
a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. Claims 1-3 and 8 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chu et al., hereafter “Chu” (U.S. Patent No. 11,901,398 B2).
Regarding claim 1, Chu discloses a display device, comprising:
a resin substrate (glass or plastic substrate 101); and
a thin-film transistor layer (200/210) provided on the resin substrate (101),
wherein the thin-film transistor layer (200/210) includes a first thin-film transistor (200) and a second thin-film transistor layer (210) both provided for each of subpixels (refers as a pixel PA, see Fig. 8 and English Text in HATSUMI A (JP-2018112679-A), the first thin-film transistor layer (200) having a first semiconductor layer (210) formed of poly silicon, and a second thin-film transistor (300) having a second semiconductor layer formed of oxide semiconductor, the first thin-film transistor (200) includes: the first semiconductor layer (210) including a first conductor region (210S) and a second conductor region (210D) defined to be spaced apart from each other; a first gate electrode (230) provided to the first semiconductor layer (210) toward the resin substrate (101) through a first gate insulating film (120), and configured to control conduction between the first conductor region (210S) and the second conductor region (210D); and a first terminal electrode (250) and a second terminal electrode (260) provided to the first semiconductor layer (210) across from the resin substrate (101), spaced apart from each other, and respectively and electrically connected to the first conductor region (210S) and the second conductor region (210D), and
the second thin-film transistor (300) includes: the second semiconductor layer (310) including a third conductor region (310S) and a fourth conductor region (310D) positioned more distant from the resin substrate (101) than the first semiconductor layer (200), and defined to be spaced apart from each other; a second gate electrode (330) provided to the second semiconductor layer (310) across from the resin substrate (101) through a second gate insulating film (150), and configured to control conduction between the third conductor region (310S) and the fourth conductor region (310D); and a third terminal electrode (350) and a fourth terminal electrode (360) provided to the second semiconductor layer (310) across from the resin substrate (101), spaced apart from each other, and respectively and electrically connected to the third conductor region (310S) and the fourth conductor region (310D) (Fig. 2 and col. 6, line 60-col. 9, line 36).
Regarding claim 2, Chu discloses wherein, on the first semiconductor layer (210), a first interlayer insulating film (140) is provided, on the first interlayer insulating film (140), the second semiconductor layer (310) is provided, on the second gate electrode (330), a second interlayer insulating film (160) is provided, he first terminal electrode (250), the second terminal electrode (260), the third terminal electrode (350), and the fourth terminal electrode (360) are provided on the second interlayer insulating film (160), the first terminal electrode (250) and the second terminal electrode (260) are respectively and electrically connected to the first conductor region (210S) and the second conductor region (210D) through a first contact hole and a second contact hole (140) formed in a multilayer film including the first interlayer insulating film (140), the second gate insulating film (150), and the second interlayer insulating film (160), and the third terminal electrode (350) and the fourth terminal electrode (360) are respectively and electrically connected to the third conductor region (310S) and the fourth conductor region (310D) through a third contact hole and a fourth contact hole formed in a multilayer film including the second gate insulating film (150) arid the second interlayer insulating film (160) (Fig. 2).
Regarding claim 3, Chu discloses wherein, on the resin substrate (101), a base coat film (102) is provided, and the first gate electrode (230) is provided on the base coat film (102) (Fig. 3).
Regarding claim 8, Chu discloses wherein the thin-film transistor layer includes a planarization film (170) provided to cover the first terminal electrode (210S), the second terminal electrode (210D), the third terminal electrode (310S), and the fourth terminal electrode (310D) (Fig. 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. Claims 4 is rejected under 35 U.S.C. 103(a) as being unpatentable over Chu in view of ZHAO D (CN-110880518-A).
Regarding claim 4, Chu discloses the features of the claimed invention as discussed above, but does not disclose wherein the first gate insulating film is thicker than the second gate insulating film.
ZHAO D, however, discloses wherein the first gate insulating film (112) is thicker than the second gate insulating film (122) (Fig. 1 and English Text).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of Chu to provide wherein the first gate insulating film is thicker than the second gate insulating film as taught by ZHAO D for a purpose of improving the gate control ability of the gate electrode.
10. Claims 5 is rejected under 35 U.S.C. 103(a) as being unpatentable over Chu in view of KIKUCHI T (WO-2018180617-A).
Regarding claim 5, Chu discloses the features of the claimed invention as discussed above, but does not disclose further comprising a conductive layer provided to the second semiconductor layer toward the resin substrate.
KIKUCHI T, however, discloses further comprising a conductive layer (9b) provided to the second semiconductor layer (21) toward the resin substrate (1) (Fig. 10 and English Text).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of Chu to provide further comprising a conductive layer provided to the second semiconductor layer toward the resin substrate as taught by KIKUCHI T for a purpose of reducing the light transmittance of the semiconductor layer.
11. Claim 6 is rejected under 35 U.S.C. 103(a) as being unpatentable over Chu in view of BAE et al., hereafter “BAE” (U.S. Publication No. 2018/0033804 A1).
Regarding claim 6, Chu discloses the features of the claimed invention as discussed above, but does not disclose wherein the conductive layer is formed of a same material as, and in a same layer as, the first gate electrode.
BAE, however, discloses wherein the conductive layer (refers as a light shielding layer (111)) is formed of a same material as, and in a same layer as, the first gate electrode (110) (Fig. 2 and claim 6).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of Chu to provide wherein the conductive layer is formed of a same material as, and in a same layer as, the first gate electrode as taught by BAE for a purpose of improving the performance for the conductive layer.
12. Claims 7 is rejected under 35 U.S.C. 103(a) as being unpatentable over Chu and KIKUCHI T in view of PARK D (KR-20180047595-A).
Regarding claim 7, Chu and KIKUCHI T discloses the features of the claimed invention as discussed above, but does not disclose wherein the conductive layer is electrically floating.
PARK D, however, discloses wherein the conductive layer (600) is electrically floating (Fig. 14 and English Text).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of Chu and KIKUCHI T to provide wherein the conductive layer is electrically floating.as taught by PARK D for a purpose of preventing light leaking from the conductive layer.
13. Claims 9-11 are rejected under 35 U.S.C. 103(a) as being unpatentable over Chu in view of WON et al., hereafter “WON” (U.S. Publication No. 2021/0200364 A1).
Regarding claim 9, Chu discloses the features of the claimed invention as discussed above, but does not disclose further comprising: a light-emitting element layer provided on the thin-film transistor layer and having a plurality of light-emitting elements arranged; and a sealing film provided to cover the light-emitting elements.
WON, however, discloses a light-emitting element layer (200) provided on the thin-film transistor layer (100) and having a plurality of light-emitting elements (210) arranged; and a sealing film (300) provided to cover the light-emitting elements (210) (Fig. 5 and para [0067]-[0068]).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of Chu to provide a light-emitting element layer provided on the thin-film transistor layer and having a plurality of light-emitting elements arranged; and a sealing film provided to cover the light-emitting elements.as taught by WON for a purpose of improving the performance for the display device.
Regarding claim 10, Chu and PARK D (citations to Chu unless otherwise noted) discloses wherein the first thin-film transistor (200) is a drive thin-film transistor configured to control a current of each of the light-emitting elements (500) (Fig. 3 and col. 11, lines 47-50).
Regarding claim 11, Chu and PARK D (citations to Chu unless otherwise noted) discloses wherein each of the light-emitting elements (500) is an organic electroluminescence element (Fig. 3).
Cited Prior Arts
14. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
ONODERA R (WO-2019130915-A) discloses a display device includes: a substrate (101); a light emitting element (240, Fig. 2); a first transistor (220 Right) wherein one of the source (207) and the drain (208) is electrically connected to the light emitting element (240), and the other one of the source (207) and the drain (208) is connected to a drive power supply line (PVDD); and a second transistor (210 Left) wherein one of the source (207) and the drain (208) is connected to the gate of the first transistor (220). The first transistor (220) includes: a first insulating layer on the substrate (101); a second insulating layer (242), which is disposed on the first insulating layer (241), and which has a film thickness that is smaller than that of the first insulating layer (241); a first semiconductor layer (221) between the first insulating layer (241) and the second insulating layer (242); a first gate electrode (217), which is disposed between the substrate (101) and the first insulating layer (241), and which has a region overlapping the first semiconductor layer (217); and a first control electrode (213), which is disposed on the second insulating layer (242), and which has a region overlapping the first semiconductor layer.(217) (Fig. 8 and English Text).
Conclusion
15. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Phuc T. Dang whose telephone number is 571-272-1776. The examiner can normally be reached on 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PHUC T DANG/Primary Examiner, Art Unit 2897
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