DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to amendment
2. This Office Action is in response to Amendment filed on 07/14/2026
Claims
Claims 1-3, 6 and 8-11 have been amended.
Claims 4-5 and 7 have been remained
Claims 1-11 are currently pending in the application.
Response to Arguments
3. Applicant's arguments with respect to claims 1-11 have been considered but are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
4. Claims 1-3 and 8 are rejected under 35 U.S.C. 103(a) as being unpatentable over Chu et al., hereafter "Chu" (U.S. Patent No. 11,901,398 B2) in view of Yang et al., hereafter “Yang” (U.S. Publication No. 2021/0193045 A1.
Regarding claim 1, Chu discloses a display device, comprising:
a resin substrate (glass or plastic substrate 101); and
a thin-film transistor layer (200/300) provided on the resin substrate (101),
wherein the thin-film transistor layer (200/300) includes a first thin-film transistor (200) and a second thin-film transistor (300) both of which provided for each of a plurality of subpixels (refers as a pixel PA, see Fig. 8 and English Text in HATSUMI A (JP-2018112679-A), the first thin-film transistor (200) having a first semiconductor layer (210) formed of poly silicon, and the second thin-film transistor (300) having a second semiconductor layer formed of oxide semiconductor,
wherein:
the first thin-film transistor (200) includes:
the first semiconductor layer (210) including a first conductor region (210S) and a second conductor region (210D) defined to be spaced apart from each other, and
a first terminal electrode (250) and a second terminal electrode (260) spaced apart from each other, and respectively and electrically connected to the first conductor region (210S) and the second conductor region (210D), and
the second thin-film transistor (300) includes:
the second semiconductor layer (310) including a third conductor region (310S) and a fourth conductor region (310D), and positioned more distant from the resin substrate (101) than the first semiconductor layer (200), the third conductor region (310S) and the fourth conductor region (310D) defined to be spaced apart from each other, and
a third terminal electrode (350) and a fourth terminal electrode (360) spaced apart from each other, and respectively and electrically, connected to the third conductor region (310S) and the fourth conductor region (310D) (Fig. 2 and col. 6, line 60-col. 9, line 36).
Chu discloses the features of the claimed invention as discussed above, but does not disclose a first gate electrode provided between the first semiconductor layer and the resin substrate, and configured to control conductivity between the first conductor region and the second conductor region, a first gate insulating film provided between the first semiconductor layer and the first gate electrode, and a second gate electrode provided on a side of the second semiconductor layer opposite the resin substrate, with a second gate insulating film interposed therebetween, and configured to control conductivity between the third conductor region (310S) and the fourth conductor region.
Yang, however, discloses a first gate electrode provided between the first semiconductor layer and the resin substrate, and configured to control conductivity between the first conductor region and the second conductor region, a first gate insulating film provided between the first semiconductor layer and the first gate electrode, and a second gate electrode provided on a side of the second semiconductor layer opposite the resin substrate, with a second gate insulating film interposed therebetween, and configured to control conductivity between the third conductor region (310S) and the fourth conductor region.
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of Chu to provide a first gate electrode provided between the first semiconductor layer and the resin substrate, and configured to control conductivity between the first conductor region and the second conductor region, a first gate insulating film provided between the first semiconductor layer and the first gate electrode, and a second gate electrode provided on a side of the second semiconductor layer opposite the resin substrate, with a second gate insulating film interposed therebetween, and configured to control conductivity between the third conductor region and the fourth conductor region as taught by Yang for a purpose of enhancing the display device performance.
Regarding claim 2, Chu and Yang (citations to Chu unless otherwise noted) discloses wherein, on the first semiconductor layer (210), a first interlayer insulating film (140) is provided, on the first interlayer insulating film (140), the second semiconductor layer (310) is provided, on the second gate electrode (330), a second interlayer insulating film (160) is provided, he first terminal electrode (250), the second terminal electrode (260), the third terminal electrode (350), and the fourth terminal electrode (360) are provided on the second interlayer insulating film (160), the first terminal electrode (250) and the second terminal electrode (260) are respectively and electrically connected to the first conductor region (210S) and the second conductor region (210D) through a first contact hole and a second contact hole (140) formed in a multilayer film including the first interlayer insulating film (140), the second gate insulating film (150), and the second interlayer insulating film (160), and the third terminal electrode (350) and the fourth terminal electrode (360) are respectively and electrically connected to the third conductor region (310S) and the fourth conductor region (310D) through a third contact hole and a fourth contact hole formed in a multilayer film including the second gate insulating film (150) arid the second interlayer insulating film (160) (Fig. 2).
Regarding claim 3, Chu and Yang (citations to Chu unless otherwise noted) discloses wherein: on the resin substrate (101), a base coat film (102) is provided, and the first gate electrode (230) is provided on the base coat film (102) (Fig. 3).
Regarding claim 8, Chu and Yang (citations to Chu unless otherwise noted) discloses wherein the thin-film transistor layer further includes a planarization film (170) provided to cover the first terminal electrode (210S), the second terminal electrode (210D), the third terminal electrode (310S), and the fourth terminal electrode (310D) (Fig. 3).
5. Claims 4 is rejected under 35 U.S.C. 103(a) as being unpatentable over Chu and Yang in view of ZHAO D (CN-110880518-A).
Regarding claim 4, Chu and Yang discloses the features of the claimed invention as discussed above, but does not disclose wherein the first gate insulating film is thicker than the second gate insulating film.
ZHAO D, however, discloses wherein the first gate insulating film (112) is thicker than the second gate insulating film (122) (Fig. 1 and English Text).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of Chu and Yang to provide wherein the first gate insulating film is thicker than the second gate insulating film as taught by ZHAO D for a purpose of improving the gate control ability of the gate electrode.
6. Claims 5 is rejected under 35 U.S.C. 103(a) as being unpatentable over Chu and Yang in view of KIKUCHI T (WO-2018180617-A).
Regarding claim 5, Chu and Yang discloses the features of the claimed invention as discussed above, but does not disclose further comprising a conductive layer provided to the second semiconductor layer toward the resin substrate.
KIKUCHI T, however, discloses further comprising a conductive layer (9b) provided to the second semiconductor layer (21) toward the resin substrate (1) (Fig. 10 and English Text).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of Chu and Yang to provide further comprising a conductive layer provided to the second semiconductor layer toward the resin substrate as taught by KIKUCHI T for a purpose of reducing the light transmittance of the semiconductor layer.
7. Claim 6 is rejected under 35 U.S.C. 103(a) as being unpatentable over Chu and Yang in view of BAE et al., hereafter “BAE” (U.S. Publication No. 2018/0033804 A1).
Regarding claim 6, Chu and Yang discloses the features of the claimed invention as discussed above, but does not disclose wherein the conductive layer is formed of a same material as, and in a same layer as, the first gate electrode.
BAE, however, discloses wherein the conductive layer (refers as a light shielding layer (111)) is formed of a same material, and in a same layer, as the first gate electrode (110) (Fig. 2 and claim 6).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of Chu and Yang to provide wherein the conductive layer is formed of a same material, and in a same layer, as the first gate electrode as taught by BAE for a purpose of improving the performance for the conductive layer.
8. Claims 7 is rejected under 35 U.S.C. 103(a) as being unpatentable over Chu, Yang and KIKUCHI T in view of PARK D (KR-20180047595-A).
Regarding claim 7, Chu, Yang and KIKUCHI T discloses the features of the claimed invention as discussed above, but does not disclose wherein the conductive layer is electrically floating.
PARK D, however, discloses wherein the conductive layer (600) is electrically floating (Fig. 14 and English Text).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of Chu, Yang and KIKUCHI T to provide wherein the conductive layer is electrically floating.as taught by PARK D for a purpose of preventing light leaking from the conductive layer.
9. Claims 9-11 are rejected under 35 U.S.C. 103(a) as being unpatentable over Chu and Yang in view of WON et al., hereafter “WON” (U.S. Publication No. 2021/0200364 A1).
Regarding claim 9, Chu and Yang discloses the features of the claimed invention as discussed above, but does not disclose further comprising: a light-emitting element layer provided on the thin-film transistor layer and having a plurality of light-emitting elements; and a sealing film provided to cover the light-emitting elements.
WON, however, discloses a light-emitting element layer (200) provided on the thin-film transistor layer (100) and having a plurality of light-emitting elements (210); and a sealing film (300) provided to cover the light-emitting elements (210) (Fig. 5 and para [0067]-[0068]).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of Chu and Yang to provide a light-emitting element layer provided on the thin-film transistor layer and having a plurality of light-emitting elements; and a sealing film provided to cover the light-emitting elements.as taught by WON for a purpose of improving the performance for the display device.
Regarding claim 10, Chu, Yang and PARK D (citations to Chu unless otherwise noted) discloses wherein the first thin-film transistor (200) is a drive thin-film transistor configured to control a current of each of the plurality of light-emitting elements (500) (Fig. 3 and col. 11, lines 47-50).
Regarding claim 11, Chu, Yang and PARK D (citations to Chu unless otherwise noted) discloses wherein each of the plurality of light-emitting elements (500) is an organic electroluminescence element (Fig. 3).
Conclusion10. Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Phuc T. Dang whose telephone number is 571-272-1776. The examiner can normally be reached on 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PHUC T DANG/Primary Examiner, Art Unit 2897
Prosecution Insights