DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 28 and 29 objected to because of the following informalities: “claims 1” should be replaced with –claim 1--. Claim 29 inherits this informality. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7 – 9, and 15 – 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chinese Published Patent Document No. CN112582464 to Zhu.
Regarding claim 1, Zhu teaches a semiconductor device, (Fig. 15(a), for example) comprising:
a vertical channel portion on a substrate (1001);
source/drain portions (S/D) respectively located at upper and lower ends of the channel portion relative to the substrate; and
a first gate stack (1037/1039) on a first side of the channel portion in a first direction lateral to the substrate and a second gate stack on a second side of the channel portion in the first direction (See Fig. 15(a)), wherein the second side is opposite to the first side, wherein a distance between an upper edge of an end of the first gate stack facing the channel portion in a vertical direction and a corresponding source/drain portion is less than a distance between a corresponding one of an upper edge and a lower edge of an end of the second gate stack facing the channel portion in the vertical direction and a corresponding source/drain portion since it is clear that the upper edge of the an end of the first gate stack is directly adjacent the corresponding source/drain portion.
Regarding claim 7, Zhu teaches a semiconductor device, wherein the first gate stack is self-aligned with the second gate stack in the first direction (Paragraph 4, of page 4 of translation).
Regarding claim 8, Zhu teaches a semiconductor device, wherein an offset of the upper edge of the end of the first gate stack facing the channel portion in the vertical direction relative to the upper edge of the end of the second gate stack facing the channel portion in the vertical direction is substantially identical to an offset of the lower edge of the end of the first gate stack facing the channel portion in the vertical direction relative to the lower edge of the end of the second gate stack facing the channel portion in the vertical direction since the two gates are identical.
Regarding claim 9, Zhu teaches a semiconductor device, further comprising:
a first semiconductor layer (1005) and a second semiconductor layer (unlabeled layer disposed on substrate) spaced apart from each other in the vertical direction; and
a third semiconductor layer (1003) extending from a sidewall of the first semiconductor layer to a sidewall of the second semiconductor layer, wherein
the channel portion is formed in a part of the third semiconductor layer located between the first semiconductor layer and the second semiconductor layer in the vertical direction, and wherein the source/drain portions are formed in the first semiconductor layer and the third semiconductor layer on the sidewall of the first semiconductor layer as well as in the second semiconductor layer and the third semiconductor layer on the sidewall of the second semiconductor layer, respectively.
Regarding claim 15, Zhu teaches a semiconductor device, wherein a gate dielectric layer (1037) in the first gate stack is only provided on the first side of the channel portion, and a gate dielectric layer (1037) in the second gate stack is only provided on the second side of the channel portion.
Regarding claim 16, Zhu teaches a semiconductor device, wherein the channel portion comprises a curved nanosheet or nanowire with a C-shape cross-section (See Fig. 15a).
Regarding claim 17, Zhu teaches a semiconductor device, wherein the curved nanosheet or nanowire has a substantially uniform thickness (Bottom of translation, page 3: “As described below, the nanosheet or nanowire can be formed by epitaxial growth, so it can be a single sheet, and may have a substantially uniform thickness.”).
Regarding claim 18, Zhu teaches a semiconductor device, wherein both ends of the channel portion in a second direction lateral to the substrate present an inward-recessed C-shape, wherein the second direction intersects with the first direction (See Fig. 15(a), for example).
Regarding claim 19, Zhu teaches a semiconductor device, wherein at least one of the channel portion and the source/drain portions comprises a single crystal semiconductor material (page 4, ¶ 3: “Of course, the source/drain part or the semiconductor layer formed by them may also include a single crystal semiconductor material.”).
Regarding claim 20, Zhu teaches a semiconductor device, wherein a plurality of semiconductor devices are provided on the substrate, and C-shapes of at least one pair of semiconductor devices among the plurality of semiconductor devices face away from each other (Fig. 25).
Regarding claim 21, Zhu teaches a semiconductor device, wherein respective channel portions of the pair of semiconductor devices are substantially coplanar (See Fig. 15).
Allowable Subject Matter
Claims 22 – 27 are allowed. Claims 28 and 29 will be allowable after correction of the informality noted above.
Claims 2 – 6, 10 – 14, 28, and 29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record does not teach or reasonably suggest a method as recited in claim 22 in particular “wherein a size of the first gate stack in the vertical direction is greater than a size of the second gate stack in the vertical direction.”
Response to Arguments
Applicant's arguments filed April 6, 2026 have been fully considered but they are not persuasive.
Applicant argues that Zhu does not teach:
wherein a distance between an upper edge of an end of the first gate stack facing the channel portion in a vertical direction and a corresponding source/drain portion is less than a distance between a corresponding one of an upper edge and a lower edge of an end of the second gate stack facing the channel portion in the vertical direction and a corresponding source/drain portion, and/or a distance between a lower edge of an end of the first gate stack facing the channel portion in a vertical direction and a corresponding source/drain portion is less than a distance between a corresponding one of an upper edge and a lower edge of an end of the second gate stack facing the channel portion in the vertical direction and a corresponding source/drain portion.
.
Examiner notes that the portion of the claim after the term “and/or” is considered optional. Both phrases can be considered, or either. Zhu teaches the first part of the phrase. This is clearly shown in Fig. 15a, which is nearly identical to Fig. 15a of the instant application. It is shown that the upper edge of the end of the first gate stack is directly adjacent the corresponding source/drain portion.
Applicant has relied on the teaching of Fig. 20 of the Zhu reference for support in arguing that Zhu does teach the claimed invention. Respectfully, Applicant’s arguments are moot since they have not addressed content of the rejection. Examiner relied on the teaching of the embodiment shown in Fig. 15a, but Applicant has argued against a different embodiment, as shown in Fig. 20. There is no rejection applied that has relied on the embodiment of Fig. 20.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS W OWENS whose telephone number is (571)272-1662. The examiner can normally be reached M-F 5:30-1:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at 571-270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
DOUGLAS W. OWENS, Esq.
Primary Patent Examiner
Art Unit 2897
/DOUGLAS W OWENS/Primary Patent Examiner, Art Unit 2897
Prosecution Insights