6DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/4/2026 has been entered.
Claims Status
Claims 8-13 are currently pending. Claims 1-7 and 14-17 were previously canceled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over NAKAI et al (US 2011/0000708 A1, hereafter Nakai) in view of KITA et al (US 2009/0243120 A1-of record, hereafter Kita).
Re Claim 8, Nakai discloses in FIG. 2: (C) (with references to FIGS. 2: (A)-(B)) a micro bump (32/34/26/32/34), comprising:
an electrically conductive material part (through-hole conductor 26; [0039]-[0040]);
a bonding material part (32/34; [0040]) provided on at least a part of an upper portion (top plane) and a lower portion (bottom plane) of the electrically conductive material part (26); and
pores (24h; [0039]) of a body (24) made of an anodic aluminum oxide film ([0024]; [0028] and [0039],
wherein a through-hole (openings for 26; [0039]) having a width (left-to-right lateral extension) greater (longer) than that of the pores (24h) is formed in the body (24) separately (distinct) from the pores (24h), and wherein the micro bump (32/34/26/32/34) is formed in the through-hole (openings for 26).
Nakai fails to disclose a plurality of fine trenches provided in an outer circumferential surface of the electrically conductive material part, the outer circumferential surface being exposed to an exterior of the micro bump,
wherein each of the plurality of fine trenches has a form of a groove extending in a height direction of the micro bump, and
wherein the plurality of fine trenches are formed as a result of contact between the micro bump and the pores of a body made of an anodic aluminum oxide film.
However,
Kita discloses in FIG. 2(A)-2(B) (with references to FIGS. 1(A)-1(B)) a micro bump (4/11/5), comprising:
an electrically conductive material part (tin of 11; [0100]; [0107] and [0189]);
a bonding material part (4/5; [0102]-[0103]) provided on at least a part of an upper portion (top plane) and a lower portion (bottom plane) of the electrically conductive material part (tin 11); and
a plurality of fine trenches (indentations/stripes of 3 on 11; [0097]; [0099]; [0108]-[0109] and [0135]-[0135]) provided in an outer circumferential surface (outermost surface) of the electrically conductive material part (tin of 11), the outer circumferential surface being exposed to an exterior (bottom of indentations/stripes of 3 on 11 in FIG. 1(B)) of the micro bump (4/11/5), wherein each of the plurality of fine trenches (indentations/stripes of 3 on 11) has a form of a groove (of Height H in FIG. 1(B)); [0109]) extending in a height direction (vertically) of the micro bump (4/11/5),
wherein the plurality of fine trenches (indentations/stripes of 3 on 11) are formed as a result of contact (physically touching when seed layer 19 is omitted; [0188]) between the micro bump (4/11/5) and a through-hole (1; [0101]) of a body made of an insulating silicon oxide film (9; [0101] and [0187]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Nakai by using the through-hole formation of Kita for the same of Nakai, overlapping with the pores of Nakai, such that a plurality of fine trenches is provided in an outer circumferential surface of the electrically conductive material part, the outer circumferential surface being exposed to an exterior of the micro bump, wherein each of the plurality of fine trenches has a form of a groove extending in a height direction of the micro bump, and wherein the plurality of fine trenches is formed as a result of contact between the micro bump and the pores of a body made of an anodic aluminum oxide film, improving the reliability of micro bump through-electrodes (Kita; [0025]; [0055] and [0140]).
Re Claim 9, Nakai and Kita discloses micro bump of claim 8, wherein the fine trenches (Kita: indentations/stripes of 3 on tin 11) are provided along (around and extending vertically upward on) the entire circumference (distance around tin 11) of the side surface (vertical walls within hole 1) of the electrically conductive material part (tin 11), as part of the through-electrodes discussed for claim 8.
Re Claim 10, Nakai discloses micro bump of claim 8, wherein the bonding material part (32/34) includes: a first bonding material part (32/34) provided on the lower portion (bottom plane) of the electrically conductive material part (26); and a second bonding material part (32/34) provided on the upper portion (top plane) of the electrically conductive material part (26).
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Nakai and Kita as applied to claim 10 above, and further in view of Lin (US 2019/0214257 A1-IDS prior art of record).
Re Claim 11, Nakai discloses the micro bump of claim 10.
But, fails to disclose the micro bump further comprising: a seed layer provided between the first bonding material part (32/34) and the electrically conductive material part (26).
However,
Lin discloses in FIG. 7 a micro bump (11/13/11; [0031]; [0037] and [0044]) comprising a seed layer (unseen lower Pd; [0038]) provided between a first bonding material part (lower 11; [0031]) and an electrically conductive material part (Sn or Au 13; [0037]-[0038]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Nakai and Kita and by using the first and second bonding parts of Lin with the electrically conductive material part of Nakai, the micro bump further comprising: a seed layer provided between the first bonding material part (32/34) and the electrically conductive material part (26), to form a micro bump selectively formed with matched electrical and mechanical properties (Lin; [0037]-[0038]).
Re Claim 12, Nakai discloses the micro bump of claim 8.
But, fails to disclose the micro bump further comprising: a functional layer provided between the electrically conductive material part (26) and the bonding material part (32/34).
However,
Lin discloses in FIG. 7 a micro bump (11/13/11; [0031]; [0037] and [0044]) comprising a seed layer (unseen upper/lower Pd; [0038]) provided between a bonding material part (upper/lower 11; [0031]) and an electrically conductive material part (Sn or Au 13; [0037]-[0038]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Nakai and Kita and by using the first and second bonding parts of Lin with the electrically conductive material part of Nakai, the micro bump further comprising: a functional layer provided between the electrically conductive material part (26) and the bonding material part (32/24), to form a micro bump selectively formed with matched electrical and mechanical properties (Lin; [0037]-[0038]).
Re Claim 13, Nakai discloses the micro bump of claim 8.
But, fails to disclose wherein the fine trenches are also provided on at least a part of a side surface of the bonding material part.
However, these limitations would be rendered obvious by the addition of the bonding material part of Lin to the electrically conductive material part of Nakai (see claims 11-12), such that the modified structure is formed within the fine trench (indentations of 3 on 11) producing through-hole (1) of Kita, as would be part of the selectively formed micro bump discussed for claims 11-12.
Response to Arguments
Applicant’s arguments with respect to claim 8 have been considered but are moot because the new ground of rejection does not rely on the same reference combination applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. For the record, arguments against the rejections of claims 9-13 are also moot in light of the new ground of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408)918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC W JONES/Primary Examiner, Art Unit 2892
Prosecution Insights