Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed November 10th, 2025 has been entered. Claims 1-20 are pending in this application. Independent claims 1, 8, and 16 have been amended to further teach DRAM integrated circuits having first and second memory access interfaces that operate independently to access non-overlapping sets of memory cores or arrays.
Applicant’s amendments to the claims have been fully considered, however the claims remain rejected for the reasons set forth below. As discussed in the 35 USC § 103 rejection made below, the prior art of record, Gregorius et al. (US 2010/0077139), hereinafter Gregorius, in view of Vijayrao et al. (US 10,684,980), hereinafter Vijayrao, further in view of Alves et al. (US 2011/0320914), in view of Alves, teaches or renders obvious the amended limitations.
Response to Arguments
Applicant's arguments filed November 10th, 2025 have been fully considered but they are not persuasive. Applicant argues that the prior art fails to teach DRAM integrated circuits having independently operating memory access interfaces that access non-overlapping sets of memory cores or arrays. This argument is not persuasive because Gregorius teaches a multi-port DRAM architecture in which respective ports of a DRAM memory device operate independently and are associated with distinct subsections of memory.
Applicant’s arguments regarding Vijayrao are also not persuasive since Vijayrao teaches an integrated memory controller having multiple independent memory channels suitable for use with a multi-port DRAM memory system. With respect to the codeword limitations, Alves teaches communicating data symbols and check symbols arranged into codewords in memory systems. Accordingly, the rejections made under 35 USC § 103 have been maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 8-11, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Vijayrao et al. (US 10,684,980), hereinafter Vijayrao, in view of Gregorius et al. (US 2010/0077139), hereinafter Gregorius, further in view of Alves et al. (US 2011/0320914), in view of Alves.
Regarding claim 1, Vijayrao teaches a controller (Vijayrao, col. 2, lines 31-34, “In various embodiments of a multi-channel DIMM system, DIMMs installed in the system are each communicatively coupled to a memory controller through multiple memory channels”), comprising: four memory channel controller interfaces to communicate with four memory channel module interfaces (Vijayrao, Fig. 2, four memory channels 230, 235, 240, 245 & DIMMs 210, 215, 220, 225, col. 5, lines 1-5, "As illustrated, the integrated memory controller supports four memory channels 230, 235, 240, and 245. Each memory channel operates independently of one another and can complete transactions concurrently") on a memory module comprising a substrate (Vijayrao, col. 4, lines 59-64, "System memory is provided by dynamic random access memory ["DRAM"] integrated circuits [not shown] mounted on dual in-line memory modules ["DIMMs"] 210, 215, 220, and 225, which are installed into DIMM sockets [not shown] on the computing system motherboard"; col. 4, line 67 through col. 5, line 1, "Each DIMM utilizes the memory channel associated with the DIMM socket into which the DIMM is installed") and a plurality of dual x2 dynamic random access memory (DRAM) integrated circuits, each disposed on the substrate (Vijayrao, col. 4, lines 59-64, “System memory is provided by dynamic random access memory ["DRAM"] integrated circuits [not shown] mounted on dual in-line memory modules ["DIMMs"] 210, 215, 220, and 225, which are installed into DIMM sockets (not shown) on the computing system motherboard”); a first memory channel controller interface of the four memory channel controller interfaces, with respective first memory access interfaces of the dual x2 DRAM integrated circuits; and a second memory channel controller interface of the four memory channel controller interfaces (Vijayrao, col. 5, lines 1-5, “As illustrated, the integrated memory controller supports four memory channels 230, 235, 240, and 245. Each memory channel operates independently of one another and can complete transactions concurrently”).
Vijayrao fails to teach the dual x2 DRAM integrated circuits each having a respective first memory access interface and a respective second memory access interface that operate independently of each other to access respective nonoverlapping sets of memory cores, first memory channel controller interface communicating first data symbols and first check symbols, arranged into first codewords, with its respective first memory access interfaces of the dual x2 DRAM devices, and the second memory channel controller interface of the four memory channel controller interfaces communicating second data symbols and second check symbols, arranged into second codewords, with its respective second memory access interfaces of the dual x2 DRAM devices.
However, Gregorius, in an analogous art, teaches the dual x2 DRAM integrated circuits each having a respective first memory access interface and a respective second memory access interface (Gregorius, Abstract, lines 1-5, “Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus”) that operate independently of each other to access respective nonoverlapping sets of memory cores (Gregorius, Abstract, lines 5-8, “Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers”).
Vijayrao and Gregorius are both considered to be analogous to the claimed invention because both are in the same field of memory systems that communicate with a plurality of memory devices or memory modules.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Vijayrao in view of Gregorius to incorporate the teachings of Gregorius by including the functionality of multi-port DRAM integrated circuits with respective memory access interfaces that allow for independent/parallel access.
The suggestion/motivation for doing so would be to decrease power consumption that might be the result of using a plurality of processors to do a respective task (Gregorius, para. [0026], lines 6-12, "While this arrangement provides flexibility to each of the processors in accessing memory for desired data, maintaining multiple memory devices may lead to increased power consumption. Furthermore, the multiple memory devices may occupy a lot of physical space, which may limit the ability to make small mobile devices with many features").
The combination of Vijayrao in view of Gregorius fails to teach the first memory channel controller interface communicating first data symbols and first check symbols, arranged into first codewords, with its respective first memory access interfaces of the dual x2 DRAM devices, and the second memory channel controller interface of the four memory channel controller interfaces communicating second data symbols and second check symbols, arranged into second codewords, with its respective second memory access interfaces of the dual x2 DRAM devices.
However, Alves, in an analogous art, teaches first data symbols and first check symbols, arranged into first codewords and second data symbols and second check symbols, arranged into second codewords (Alves, Fig. 4, para. [0030], lines 1-8, "In the RAIM store path depicted in FIG. 4, the ECC generator 404 receives store data 402 and outputs five groupings of channel data 406 that include ECC checkbits. The channel data 406 are input to individual CRC generators 408 to generate CRC bits for the channel data 406, Output from the CRC generators 408 [including CRC and data and ECC bits] are then output to the downstream bus 104 [or channel] for transmission to the memory modules 102").
Vijayrao, Gregorius, and Alves are considered to be analogous to the claimed invention because they are in the same field of memory systems that communicate with a plurality of memory devices or memory modules.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Vijayrao in view of Gregorius to incorporate the teachings of Alves by including the functionality of communicating data symbols and check symbols, arranged into codewords.
The suggestion/motivation for doing so would be to improve the reliability of the transmitted data and to transmit information about any errors that exist in the data (Alves, para. [0003], lines 7-14, "The number of errors that can be detected, pinpointed, and corrected is related to the length of the ECC field appended to the data word. ECC techniques have been used to improve availability of storage systems by correcting memory device ( e.g., dynamic random access memory or "DRAM") failures so that customers do not experience data loss or data integrity issues due to failure of a memory device").
Regarding claim 2, the combination of Vijayrao in view of Gregorius, further in view of Alves, teaches the controller of claim 1, comprising: error detection and correction circuitry to process the first codewords to determine whether there are errors in the first codewords (Alves, Abstract, lines 1-8, "Error correction and detection in a redundant memory system that includes a memory controller; a plurality of memory channels in communication with the memory controller, the memory channels including a plurality of memory devices ...and an error correction code (ECC) mechanism").
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Vijayrao in view of Gregorius to incorporate the teachings of Alves by including the functionality of error detection and correction circuity to determine if there are errors in the codewords.
The suggestion/motivation for doing so would be to prevent data loss caused by device failure (Alves, para. [0003], lines 9-14, “ECC techniques have been used to improve availability of storage systems by correcting memory device [e.g., dynamic random access memory or "DRAM"] failures so that customers do not experience data loss or data integrity issues due to failure of a memory device”).
Regarding claim 3, the combination of Vijayrao in view of Gregorius, further in view of Alves, teaches the controller of claim 2, wherein the first data symbols and the first check symbols have 4 bits (Vijayrao, col. 5, lines 47-48, "However, other data widths per DRAM IC, number of DRAM ICs, and DIMM socket data widths may be used").
Regarding claim 4, the combination of Vijayrao in view of Gregorius, further in view of Alves, teaches the controller of claim 2, comprising: persistent error detection circuitry to determine whether errors in the first codewords are persistent (Alves, para. [0036], lines 1-8, "The RAIM ECC code supports incorporating a special uncorrectable error (SPUE) signature into an encoded data packet so that in the absence of new errors, and irrespective of the chip and channel marking state and the errors in the marked chips/channel, the SPUE is still detectable as a SPUE. Even if there are a large number of errors on top of the codeword, the data will still be flagged as a UE").
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Vijayrao in view of Gregorius to incorporate the teachings of Alves by including the functionality of having persistent error detection capabilities.
The suggestion/motivation for doing so would be to distinguish errors that are uncorrectable from clean data or correctable errors (Alves, para. [0036], lines 8-11, "This is necessary to protect against UE data that has to be stored to memory to keep soft errors from having that data appear good [i.e. Clean or CE]").
Regarding claim 8, Vijayrao teaches a memory controller (Vijayrao, col. 2, lines 31-34, “In various embodiments of a multi-channel DIMM system, DIMMs installed in the system are each communicatively coupled to a memory controller through multiple memory channels”), comprising: a first memory channel to communicate, with a first independent channel of a plurality of dual independent channel dynamic random access memory (DRAM) integrated circuits (Vijayrao, Fig. 2, four memory channels 230, 235, 240, 245 & DIMMs 210, 215, 220, 225, col. 5, lines 1-5, "As illustrated, the integrated memory controller supports four memory channels 230, 235, 240, and 245. Each memory channel operates independently of one another and can complete transactions concurrently") each disposed on a single substrate of a memory module (Vijayrao, col. 4, lines 59-64, "System memory is provided by dynamic random access memory ["DRAM"] integrated circuits [not shown] mounted on dual in-line memory modules ["DIMMs"] 210, 215, 220, and 225, which are installed into DIMM sockets [not shown] on the computing system motherboard"; col. 4, line 67 through col. 5, line 1, "Each DIMM utilizes the memory channel associated with the DIMM socket into which the DIMM is installed"), and a second memory channel to communicate, with a second independent channel of the plurality of dual independent channel DRAM integrated circuits disposed on the substrate (Vijayrao et al. (US 10,684,980), Fig. 2, four memory channels 230, 235, 240, 245, col. 5, lines 1-5, "As illustrated, the integrated memory controller supports four memory channels 230, 235, 240, and 245. Each memory channel operates independently of one another and can complete transactions concurrently").
Vijayrao fails to teach each dual independent channel DRAM integrated circuit having a respective first memory access interface and a respective second memory access interface that operate independently of each other to access non-overlapping sets of memory arrays, first data symbol fields and first check symbol fields, arranged into first codewords and second data symbol fields and second check symbol fields, arranged into second codewords.
However, Gregorius, in an analogous art, teaches each dual independent channel DRAM integrated circuit having a respective first memory access interface and a respective second memory access interface (Gregorius, Abstract, lines 1-5, “Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus”) that operate independently of each other to access non-overlapping sets of memory arrays (Gregorius, Abstract, lines 5-8, “Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers”).
Vijayrao and Gregorius are both considered to be analogous to the claimed invention because both are in the same field of memory systems that communicate with a plurality of memory devices or memory modules.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Vijayrao in view of Gregorius to incorporate the teachings of Gregorius by including the functionality of dual independent channel DRAM integrated circuits with respective memory access interfaces that allow for independent/parallel access.
The suggestion/motivation for doing so would be to decrease power consumption that might be the result of using a plurality of processors to do a respective task (Gregorius, para. [0026], lines 6-12, "While this arrangement provides flexibility to each of the processors in accessing memory for desired data, maintaining multiple memory devices may lead to increased power consumption. Furthermore, the multiple memory devices may occupy a lot of physical space, which may limit the ability to make small mobile devices with many features").
The combination of Vijayrao in view of Gregorius fails to teach first data symbols and first check symbols, arranged into first codewords and second data symbols and second check symbols, arranged into second codewords
However, Alves, in an analogous art, teaches first data symbols and first check symbols, arranged into first codewords and second data symbols and second check symbols, arranged into second codewords (Alves, Fig. 4, para. [0030], lines 1-8, "In the RAIM store path depicted in FIG. 4, the ECC generator 404 receives store data 402 and outputs five groupings of channel data 406 that include ECC checkbits. The channel data 406 are input to individual CRC generators 408 to generate CRC bits for the channel data 406, Output from the CRC generators 408 [including CRC and data and ECC bits] are then output to the downstream bus 104 [or channel] for transmission to the memory modules 102").
Vijayrao, Gregorius, and Alves are considered to be analogous to the claimed invention because they are in the same field of memory systems that communicate with a plurality of memory devices or memory modules.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Vijayrao in view of Gregorius to incorporate the teachings of Alves by including the functionality of communicating data symbols and check symbols, arranged into codewords.
The suggestion/motivation for doing so would be to improve the reliability of the transmitted data and to transmit information about any errors that exist in the data (Alves, para. [0003], lines 7-14, "The number of errors that can be detected, pinpointed, and corrected is related to the length of the ECC field appended to the data word. ECC techniques have been used to improve availability of storage systems by correcting memory device ( e.g., dynamic random access memory or "DRAM") failures so that customers do not experience data loss or data integrity issues due to failure of a memory device").
Regarding claim 9, the combination of Vijayrao in view of Gregorius, further in view of Alves, teaches the memory controller of claim 8, further comprising: error detection and correction circuitry to, based on values in at least one of the first check symbol fields, correct an error in a first one of the first data symbol fields (Alves, Abstract, lines 1-8, "Error correction and detection in a redundant memory system that includes a memory controller; a plurality of memory channels in communication with the memory controller, the memory channels including a plurality of memory devices ...and an error correction code (ECC) mechanism").
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Vijayrao in view of Gregorius to incorporate the teachings of Alves by including the functionality of error detection and correction circuity to determine if there are errors in the symbol fields.
The suggestion/motivation for doing so would be to prevent data loss caused by device failure (Alves, para. [0003], lines 9-14, “ECC techniques have been used to improve availability of storage systems by correcting memory device [e.g., dynamic random access memory or "DRAM"] failures so that customers do not experience data loss or data integrity issues due to failure of a memory device”).
Regarding claim 10, the combination of Vijayrao in view of Gregorius, further in view of Alves, teaches the memory controller of claim 8, wherein each of the plurality of dual independent channel DRAM devices communicates using a data width of two bits of data with each of the first memory channel and the second memory channel (Vijayrao, col. 5, lines 47-48, "However, other data widths per DRAM IC, number of DRAM ICs, and DIMM socket data widths may be used").
Regarding claim 11, the combination of Vijayrao in view of Gregorius, further in view of Alves, teaches the memory controller of claim 10, wherein each of the first data symbol fields, first check symbol fields, second data symbol fields, and second check symbol fields are four bit wide fields (Vijayrao, col. 5, lines 47-48, "However, other data widths per DRAM IC, number of DRAM ICs, and DIMM socket data widths may be used").
Claim 16 is a method with limitations similar to the memory controller of claim 8, and is rejected under the same rationale.
Regarding claim 17, the combination of Vijayrao in view of Gregorius, further in view of Alves, teaches the method of claim 16, further comprising: based on a first value of a third codeword received via the first independent channel, correcting an error in the first value (Alves, Abstract, lines 1-8, "Error correction and detection in a redundant memory system that includes a memory controller; a plurality of memory channels in communication with the memory controller, the memory channels including a plurality of memory devices ...and an error correction code (ECC) mechanism").
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Vijayrao in view of Gregorius to incorporate the teachings of Alves by including the functionality of error detection and correction circuity to determine if there are errors in the codewords.
The suggestion/motivation for doing so would be to prevent data loss caused by device failure (Alves, para. [0003], lines 9-14, “ECC techniques have been used to improve availability of storage systems by correcting memory device [e.g., dynamic random access memory or "DRAM"] failures so that customers do not experience data loss or data integrity issues due to failure of a memory device”).
Allowable Subject Matter
Claims 5-7, 12-15, and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kwon et al. (US 2018/0285252) teaches a memory system that is divided into a plurality of subsections, where each subsection is coupled to an independent memory channel to a memory controller.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/G.V.B./Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112