DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The new title submitted 6/1/2026 is acknowledged and accepted by the Office.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/27/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant’s arguments, see pages 7-10, filed 6/1/2026, with respect to the rejection(s) of independent claim(s) 1; and 2 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, their rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of KA et al (US 2017/0345367 A1) in view of LEE et al (US 2009/0200544 A1) and MOU et al (US 2021/0376026 A1-of record). For the record, the argument of claims 4-11 being allowable due to the deficiencies of Mou and/or Nakamura is moot in light of the new ground(s) of rejection being presented.
Claims Status
Claims 1, 2 and 4-11 are currently pending and being examined. Claim 3 is now canceled.
Claim Objections
Claims 1-2 and 4-11 are objected to because of the following informalities:
A. The grammatical error: “the pixel” in line 8 of Claim 1 should read as “the pixels”.
B. The grammatical error: “the pixel” in line 8 of Claim 2 should read as “the pixels”. Appropriate correction is required.
In Re claims 4-11, they are objected to due to their dependence from claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, 7-11; and 2 are rejected under 35 U.S.C. 103 as being unpatentable over KA et al (US 2017/0345367 A1, hereafter Ka) in view of LEE et al (US 2009/0200544 A1, hereafter Lee) and MOU et al (US 2021/0376026 A1-of record, hereafter Mou).
Re claim 1, Ka discloses in FIGS. 3, 7 and 11A a display device comprising:
a substrate layer (102; [0080];
a thin-film transistor layer (transistors T1-T7 of 11A for each pixel; [0004] and [0161]) provided on the substrate layer (102); and
a light-emitting element layer (OLEDs for each pixel electrically connected to transistors T1-T7 of 11A; [0029]) provided on the thin-film transistor layer (transistors T1-T7 of 11A for each pixel), wherein:
the light-emitting element layer (OLEDs for each pixel electrically connected to transistors T1-T7 of 11A) includes a light-emitting element provided (OLED of upper right PXL2 in PA2; [0109]-[0114]) in a first subpixel (upper left PXL2 in PA2; [0112]) of a plurality of subpixels (PXL1 of PA1/PXL2 of PA2/PXL3 of PA3; [0110]-[0113]) forming a display region (PA1/PA2/PA3),
the thin-film transistor layer (transistors T1-T7 of 11A for each pixel) includes a plurality of thin-film transistors (transistors T1-T7 of 11A for each pixel; [0004] and [0164]) provided in the subpixels (PXL1/PXL2/PXL3),
the plurality of thin-film transistors (transistors T1-T7 of 11A for each pixel) is configured to control an operation ([0164]-[0173]) of the light-emitting element (OLED of upper left PXL2 in PA2) to display an image ([0075]) in the display region (PA1/PA2/PA3) by a light emission (R/G/B; [0278]) from the light-emitting element (OLED of upper right PXL2 in PA2),
the first subpixel (upper right PXL2 in PA2) of the plurality of subpixels (PXL1/PXL2/PXL3) is located in a middle (see inserted figure below) of the display region (PA1/PA2/PA3), and a second subpixel (rightmost PXL1 of 2nd row in PA1) of the plurality of subpixels (PXL1/PXL2/PXL3) is located at an outer edge (see inserted figure below) of the display region (PA1/PA2/PA3),
each of the first subpixel (upper right PXL2 in PA2) and the second subpixel (lower left PXL1 in PA1) is configured as one of a red subpixel ([0278]), a green subpixel ([0278]), and a blue subpixel ([0278]),
a first thin-film transistor (control transistor of PA2; [0009]) is included in the plurality of thin-film transistors (transistors T1-T7 of 11A for each pixel) provided in the first subpixel (upper right PXL2 in PA2) and a second thin-film transistor (control transistor of PA1; [0009]) is included in the plurality of thin-film transistors (transistors T1-T7 of 11A for each pixel) provided in the second subpixel (lower left PXL1 in PA1), and
the first thin-film transistor (control transistor of PA2) and the second thin-film transistor (control transistor of PA1) have an identical function (same function; [0006]), and
a channel length ([0006]) of the second thin-film transistor (control transistor of PA1) is different than ([0006]) a channel length ([0006]) of the first thin-film transistor (control transistor of PA2).
Ka fails to disclose the first subpixel (upper right PXL2 in PA2) and the second subpixel (lower left PXL1 in PA1) have an identical emission color, and a channel length of the second thin-film transistor is shorter than a channel length of the first thin-film transistor.
However,
A. Lee discloses in FIG. 2 a display device comprising: a pixel arrangement of red, green, blue and white pixels (R, G, B and W; [0045]), where the location of the pixels may vary ([0046]).
And,
B. Mou discloses in FIG. 1A a display device comprising: a first driving transistor (111; [0054) and a second driving transistor (121; [0054]) having the same channel widths ([0054]) and different channel lengths ([0054]), satisfying the expression W1/L1>W2/L2 ([0054]).
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For the record, the inserted figure (annotated FIG. 7 of Ka with FIG. 2 of Lee) depicts the pixel arrangement of Lee applied to the pixel areas (PA1/PA2/PA3) of Ka, where PA2 is the middle of display region (PA1/PA2/PA3), and the rightmost side of the outer edge of display region (PA1/PA2/PA3).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Ka by: firstly, using the pixel arrangement of Lee with the first and second subpixels of Ka, such that the first subpixel (upper right PXL2 in PA2) and the second subpixel (lower left PXL1 in PA1) have an identical emission color, where luminance is enhanced by the addition of white subpixels (Lee; [0045]).
And secondly, using the wide-to-length (W/L) of Mou, where the widths are the same (W1=W2), leading to the first length being less than the second length (L1<L2), and applying this relationship to the first and second subpixels of Ka, leading to the channel length of the second thin-film transistor is shorter than a channel length of the first thin-film transistor, when L1 is used as the channel length of the second thin-film transistor and L2 is used as the channel length of the first thin-film transistor, where a phenomenon of insufficient brightness of blue light is avoided, so that the white balance color coordinate of the white light at the highest gray level can be avoided from deviating from the design value ([0056]-[0058]).
Re claim 2, Ka discloses in FIGS. 3, 7 and 11A a display device comprising:
a substrate layer (102; [0080];
a thin-film transistor layer (transistors T1-T7 of 11A for each pixel; [0004] and [0161]) provided on the substrate layer (102); and
a light-emitting element layer (OLEDs for each pixel electrically connected to transistors T1-T7 of 11A; [0029]) provided on the thin-film transistor layer (transistors T1-T7 of 11A for each pixel), wherein:
the light-emitting element layer (OLEDs for each pixel electrically connected to transistors T1-T7 of 11A) includes a light-emitting element provided (OLED of upper right PXL2 in PA2; [0109]-[0114]) in a first subpixel (upper left PXL2 in PA2; [0112]) of a plurality of subpixels (PXL1 of PA1/PXL2 of PA2/PXL3 of PA3; [0110]-[0113]) forming a display region (PA1/PA2/PA3),
the thin-film transistor layer (transistors T1-T7 of 11A for each pixel) includes a plurality of thin-film transistors (transistors T1-T7 of 11A for each pixel; [0004] and [0164]) provided in the subpixels (PXL1/PXL2/PXL3),
the plurality of thin-film transistors (transistors T1-T7 of 11A for each pixel) is configured to control an operation ([0164]-[0173]) of the light-emitting element (OLED of upper right PXL2 in PA2) to display an image ([0075]) in the display region (PA1/PA2/PA3) by a light emission (R/G/B; [0278]) from the light-emitting element (OLED of upper right PXL2 in PA2),
the first subpixel (upper right PXL2 in PA2) of the plurality of subpixels (PXL1/PXL2/PXL3) is located in a middle (see inserted figure above) of the display region (PA1/PA2/PA3), and a second subpixel (rightmost PXL1 of 2nd row in PA1) of the plurality of subpixels (PXL1/PXL2/PXL3) is located at an outer edge (see inserted figure above) of the display region (PA1/PA2/PA3),
each of the first subpixel (upper right PXL2 in PA2) and the second subpixel (lower left PXL1 in PA1) is configured as one of a red subpixel ([0278]), a green subpixel ([0278]), and a blue subpixel ([0278]),
a first thin-film transistor (control transistor of PA2; [0009]) is included in the plurality of thin-film transistors (transistors T1-T7 of 11A for each pixel) provided in the first subpixel (upper right PXL2 in PA2) and a second thin-film transistor (control transistor of PA1; [0009]) is included in the plurality of thin-film transistors (transistors T1-T7 of 11A for each pixel) provided in the second subpixel (lower left PXL1 in PA1), and
the first thin-film transistor (control transistor of PA2) and the second thin-film transistor (control transistor of PA1) have an identical function (same function; [0006]), and
a channel width ([0006]) of the second thin-film transistor (control transistor of PA1) is different than ([0006]) a channel width ([0006]) of the first thin-film transistor (control transistor of PA2).
Ka fails to disclose the first subpixel (upper right PXL2 in PA2) and the second subpixel (lower left PXL1 in PA1) have an identical emission color, and a channel width of the second thin-film transistor is shorter than a channel width of the first thin-film transistor.
However,
A. Lee discloses in FIG. 2 a display device comprising: a pixel arrangement of red, green, blue and white pixels (R, G, B and W; [0045]), where the location of the pixels may vary ([0046]).
And,
B. Mou discloses in FIG. 1A a display device comprising: a first driving transistor (111; [0054) and a second driving transistor (121; [0054]) having the same channel lengths ([0054]) and different channel widths ([0054]), satisfying the expression W1/L1>W2/L2 ([0054]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Ka by: firstly, using the pixel arrangement of Lee with the first and second subpixels of Ka, such that the first subpixel (upper right PXL2 in PA2) and the second subpixel (lower left PXL1 in PA1) have an identical emission color, where luminance is enhanced by the addition of white subpixels (Lee; [0045]).
And secondly, using the wide-to-length (W/L) of Mou, where the widths are the same (L1=L2), leading to the first length being less than the second length (W1>W2), and applying this relationship to the first and second subpixels of Ka, leading to the channel width of the second thin-film transistor is wider than a channel width of the first thin-film transistor, when W1 is used as the channel width of the second thin-film transistor and W2 is used as the channel width of the first thin-film transistor, where a phenomenon of insufficient brightness of blue light is avoided, so that the white balance color coordinate of the white light at the highest gray level can be avoided from deviating from the design value ([0056]-[0058]).
Re claim 4, Ka and Lee and Mou disclose the display device according to claim 1, wherein: the plurality of subpixels further includes a third subpixel (upper right PXL2 of PA2; see inserted figure above) located at a position on the outer edge other than a corner of the display region, and a fourth subpixel (lower right PXL1 of PA1; see inserted figure above) located at the corner on the outer edge of the display region (PA1/PA2/PA3),
the third subpixel (upper right PXL2 of PA2) and the fourth subpixel (lower right PXL1 of PA1) have an identical emission color (B; see inserted figure above),
a third thin-film transistor (control transistor of PA2; [0009]) is included in the plurality of thin-film transistors (transistors T1-T7 of 11A for each pixel) provided in the third subpixel and a fourth thin-film transistor (control transistor of PA1; [0009]) is included in the plurality of thin-film transistors (transistors T1-T7 of 11A for each pixel) provided in the fourth subpixel,
the third thin-film transistor (control transistor of PA2) and the fourth thin-film transistor (control transistor of PA2) have an identical function ([0006]), and
a channel length of the fourth thin-film transistor is shorter than a channel length of the third thin-film transistor (see claim Mou for claim 1).
Re claim 5, Ka and Lee and Mou disclose the display device according to claim 1, wherein: the plurality of subpixels further includes a third subpixel (upper right PXL2 of PA2; see inserted figure above) located at a position on the outer edge other than a corner of the display region, and a fourth subpixel (lower right PXL1 of PA1; see inserted figure above) located at the corner on the outer edge of the display region (PA1/PA2/PA3),
the third subpixel (upper right PXL2 of PA2) and the fourth subpixel (lower right PXL1 of PA1) have an identical emission color (B; see inserted figure above),
a third thin-film transistor (control transistor of PA2; [0009]) is included in the plurality of thin-film transistors (transistors T1-T7 of 11A for each pixel) provided in the third subpixel and a fourth thin-film transistor (control transistor of PA1; [0009]) is included in the plurality of thin-film transistors (transistors T1-T7 of 11A for each pixel) provided in the fourth subpixel,
the third thin-film transistor (control transistor of PA2) and the fourth thin-film transistor (control transistor of PA2) have an identical function ([0006]), and
a channel width of the fourth thin-film transistor is wider than a channel width of the third thin-film transistor (see claim Mou for claim 2).
Re claim 7, Ka and Lee and Mou disclose the display device according to claim 1, wherein channel lengths of the plurality of thin-film transistors (transistors T1-T7 for PA2) around an outer periphery (leftmost edge of PA2) of the display region (PA1/PA2/PA3) decrease (diagonally) from the middle (PA2) of the display region (PA1/PA2/PA3) to the outer edge (rightmost edge of PA1) of the display region (PA1/PA2/PA3).
Re claim 8, Ka and Lee and Mou disclose the display device according to claim 1.
But, fail to disclose wherein channel widths of the plurality of thin-film transistors around an outer periphery of the display region increase from the middle of the display region to the outer edge of the display region.
However,
A. Ka discloses first driving transistors and second driving transistors with at least one of a channel width and a channel length of the first transistor is different from at least one of a channel width and a channel length of the second transistor ([0006]).
And,
B. Mou discloses the first driving transistor (111) and the second driving transistor (121), where the channel widths and channel lengths of the first driving transistor and the second driving transistor are all different ([0054]). Also, a channel width-length ratio of a third driving transistor (131) is less than ([0146]) the channel width-length ratio of the first driving transistor (111).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Ka with its and Mou’s disclosures of first and second driving transistors of different widths and/or lengths, to configure the display region wherein channel widths of the plurality of thin-film transistors around an outer periphery of the display region increase from the middle of the display region to the outer edge of the display region, wherein a phenomenon of insufficient brightness of blue light is avoided, so that the white balance color coordinate of the white light at the highest gray level can be avoided from deviating from the design value ([0056]-[0058]).
Re claims 9 and 10, Ka discloses the display device according to claim 1.
But, fails to disclose wherein the plurality of thin-film transistors includes a polysilicon thin-film transistor having a semiconductor layer composed of polysilicon, and an oxide thin-film transistor having a semiconductor layer composed of an oxide semiconductor; and wherein the second thin-film transistor has a semiconductor layer composed of an oxide semiconductor.
However, Mou discloses wherein a plurality of thin-film transistors include polysilicon or oxide semiconductor thin film transistors ([0166]); and wherein the at least one thin-film transistor (111/121/131) has a semiconductor layer (active layer; [0006]) composed of an oxide semiconductor ([0166]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Ka, using the thin-film transistor types of Mou, to provide the plurality of thin-film transistors to include a first thin-film transistor having a semiconductor layer composed of polysilicon, and a second thin-film transistor having a semiconductor layer composed of an oxide semiconductor, as substitutional equivalents (MPEP § 2144.06) for providing switching devices with the same characteristics ([0166]).
Re claim 11, Ka discloses the display device according to claim 1, wherein the light-emitting element (OLED of upper right PXL2 in PA2) is an organic electroluminescence element ([0110]-[0111] and [0113]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ka and Lee and Mou as applied to claim 1 above, and further in view of Nakamura et al (US 2017/0069664 A1-of record, hereafter Nakamura).
Re claim 6, Ka and Lee and Mou disclose the display device according to claim 1, wherein: the plurality of subpixels further includes a third subpixel (upper right PXL2 of PA2; see inserted figure above) located at a position on the outer edge other than a corner of the display region, and a fourth subpixel (lower right PXL1 of PA1; see inserted figure above) located at the corner on the outer edge of the display region (PA1/PA2/PA3),
a third thin-film transistor (control transistor of PA2; [0009]) is included in the plurality of thin-film transistors (transistors T1-T7 of 11A for each pixel) provided in the third subpixel and a fourth thin-film transistor (control transistor of PA1; [0009]) is included in the plurality of thin-film transistors (transistors T1-T7 of 11A for each pixel) provided in the fourth subpixel,
the third thin-film transistor (control transistor of PA2) and the fourth thin-film transistor (control transistor of PA2) have an identical function ([0006]),
But, fail to disclose and the third thin-film transistor has a single-gate structure and the fourth thin-film transistor has a multi-gate structure.
However,
Nakamura discloses in FIGS. 1A-1C and 17 a display device (100) comprising a first driving transistor (70b; [0254]) can be a single-gate transistor ([0254]) and a second driving transistor (70c; [0254]) can be a dual-gate transistor ([0254]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention modify the structure of Mou by providing the dual-gate transistors of Nakamura, wherein at least one of the plurality of thin-film transistors provided in the second subpixel is a thin-film transistor of multi-gate structure, and wherein one of the plurality of thin-film transistors provided in the first subpixel and having a function identical to that of the thin-film transistor of multi-gate structure in the second subpixel is a thin-film transistor of single-gate structure, where a dual-gate transistor can be used as a transistor in which a higher current desirably flows, while single-gate transistors are used as the other transistors. For example, a W/L ratio between the channel length (L) and the channel width (W) of a transistor in which a higher current desirably flows can be made larger than the W/L ratio of the other transistors (Nakamura; [0156] and [0254]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408) 918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
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/ERIC W JONES/
Primary Examiner, Art Unit 2892
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