Prosecution Insights
Last updated: April 19, 2026
Application No. 18/571,601

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Non-Final OA §102§103
Filed
Dec 18, 2023
Examiner
GREEN, TELLY D
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Csmc Technologies Fab2 Co. Ltd.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
85%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
1044 granted / 1280 resolved
+13.6% vs TC avg
Minimal +4% lift
Without
With
+3.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
48 currently pending
Career history
1328
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
54.2%
+14.2% vs TC avg
§102
25.3%
-14.7% vs TC avg
§112
12.9%
-27.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1280 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 11, 14 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (Wang) (CN 103972164 A).. In regards to claim 11, Wang (Fig. 7 and associated text) discloses a semiconductor device (Fig. 7) comprising: a substrate (item 10); a dielectric layer (items 20 plus 30 plus 40 plus 60) comprising an etching stop layer (item 20), a first dielectric layer (item 30), an auxiliary dielectric layer (item 40), and a second dielectric layer (item 60) that are successively stacked from bottom to top on the substrate (item 10); and a first (upper portion where item 70 resides with greater width) and a second trench (bottom portion where item 70 resides with lesser width) located in the dielectric layer (items 20 plus 30 plus 40 plus 60), wherein the first trench (upper portion where item 70 resides with greater width) extends downward from an upper surface of the dielectric layer (items 20 plus 30 plus 40 plus 60), and a trench depth of the first trench (upper portion where item 70 resides with greater width) is less than a thickness of the dielectric layer (items 20 plus 30 plus 40 plus 60), wherein the second trench (bottom portion where item 70 resides with lesser width) extends downward from a bottom surface of the first trench (upper portion where item 70 resides with greater width) and extends through the dielectric layer (items 20 plus 30 plus 40 plus 60), and the first trench (upper portion where item 70 resides with greater width) and the second trench (bottom portion where item 70 resides with lesser width) are provided with a conductive layer (items 70) therein, wherein a bottom of the first trench (bottom of upper portion where item 70 resides with greater width) is located in the first dielectric layer (item 30), and the second trench (bottom portion where item 70 resides with lesser width) extends through parts of the first dielectric layer (item 30) and the etching stop layer (item 20). In regards to claim 14, Wang (Fig. 7 and associated text) discloses wherein a material of the conductive layer (item 70) comprises at least one of Cu, W, Al, Ag and Au (paragraph 4, Wang), and the conductive layer (item 70, Wang) serves as a conductive interconnection layer. Examiner notes that “serve as a conductive interconnection layer” is intended use language. It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiated the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations (Ex parte Mashim, 2 USPQ2d 1647 (1987)). In regards to claim 15, Wang (Fig. 7 and associated text) discloses wherein the trench depth of the first trench (upper portion where item 70 resides with greater width, Wang) is greater than a trench depth of the second trench (bottom portion where item 70 resides with lesser width). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (Wang) (CN 103972164 A) in view of Kaltalioglu (US 2002/0173079 A1). In regards to claim 12, Wang does not specifically disclose wherein the second trench is located at an edge of a bottom of the first trench. Kaltalioglu (Fig. 8 and associated text) discloses wherein the second trench (item 48) is located at an edge of a bottom of the first trench (item 66). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Kaltalioglu for the purpose of an interconnect, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)). In regards to claim 13, Wang as modified by Kaltalioglu (Fig. 8 and associated text) discloses wherein one sidewall of the second trench (item 48) is connected to a sidewall of the first trench (item 66), and the other sidewall of the second trench (item 48) is spaced apart from the sidewall of the first trench (item 66). Claim(s) 11, 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wann et al. (Wann) (US 2013/0015581 A1) in view of Wang et al. (Wang) (CN 103972164 A). In regards to claim 11, Wann (Figs. 1, 9 and associated text and items) discloses a semiconductor device (items 50, 250) comprising: a substrate (item 52); a dielectric layer (items 62 plus 60 plus 68 plus 66) comprising an etching stop layer (item 62), a first dielectric layer (item 60), an auxiliary dielectric layer (item 68), and a second dielectric layer (item 66) that are successively stacked from bottom to top on the substrate (item 52); and a first trench (item 258 which is where item 262 resides) and a second trench (item 252, where item 256 resides) located in the dielectric layer (items 62 plus 60 plus 68 plus 66), wherein the first trench (item 258 which is where item 262 resides) extends downward from an upper surface of the dielectric layer (items 62 plus 60 plus 68 plus 66), and a trench depth of the first trench (item 258 which is where item 262 resides) is less than a thickness of the dielectric layer (items 62 plus 60 plus 68 plus 66), wherein the second trench (item 252, where item 256 resides) extends downward from a bottom surface of the first trench (item 258 which is where item 262 resides) and extends through the dielectric layer (items 62 plus 60 plus 68 plus 66), and the first trench (item 258 which is where item 262 resides) and the second trench (item 252, where item 256 resides) are provided with a conductive layer (items 256, 262) therein, the second trench (item 252, where item 256 resides) extends through parts of the first dielectric layer (item 60) and the etching stop layer (item 62), but does not specifically disclose wherein a bottom of the first trench is located in the first dielectric layer, and the second trench extends through parts of the first dielectric layer and the etching stop layer. Wang (Fig. 7 and associated text) discloses wherein a bottom of the first trench (bottom of upper portion where item 70 resides with greater width) is located in the first dielectric layer (item 30), and the second trench (bottom portion where item 70 resides with lesser width) extends through parts of the first dielectric layer (item 30) and the etching stop layer (item 20). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Wang for the purpose of an electrical connection and/or interconnect (abstract, paragraph 14), since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)). In regards to claim 14, Wann (Figs. 1, 9 and associated text and items) and Wang (Fig. 7 and associated text) both disclose wherein a material of the conductive layer (items 256, 262, Wann, item 70, Wang) comprises at least one of Cu, W, Al, Ag and Au (paragraph 62, Wann, paragraph 4, Wang), and the conductive layer (items 256, 262, Wann, item 70, Wang) serves as a conductive interconnection layer. Examiner notes that “serve as a conductive interconnection layer” is intended use language. It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiated the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations (Ex parte Mashim, 2 USPQ2d 1647 (1987)). In regards to claim 15, Wann (Figs. 1, 9 and associated text and items) as modified by Wang (Fig. 7 and associated text) discloses wherein the trench depth of the first trench (item 258 which is where item 262 resides , Wann, bottom of upper portion where item 70 resides with greater width, Wang) is greater than a trench depth of the second trench (item 252, where item 256 resides, Wann, bottom portion where item 70 resides with lesser width, Wang). Claim(s) 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wann et al. (Wann) (US 2013/0015581 A1) in view of Wang et al. (Wang) (CN 103972164 A) as applied to claims 11, 14 and 15 above, and further in view of Kaltalioglu (US 2002/0173079 A1). In regards to claim 12, Wann (Figs. 1, 9 and associated text and items) discloses wherein the second trench (item 252, where item 256 resides) is located near an edge of a bottom of the first trench (item 258 which is where item 262 resides), but does not specifically disclose wherein the second trench is located at an edge of a bottom of the first trench. Kaltalioglu (Fig. 8 and associated text) discloses wherein the second trench (item 48) is located at an edge of a bottom of the first trench (item 66). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Kaltalioglu for the purpose of an interconnect, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)). In regards to claim 13, Wann as modified by Wang and Kaltalioglu (Fig. 8 and associated text) discloses wherein one sidewall of the second trench (item 48) is connected to a sidewall of the first trench (item 66), and the other sidewall of the second trench (item 48) is spaced apart from the sidewall of the first trench (item 66). Allowable Subject Matter Claims 1-10 are allowed. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See all References listed 892. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TELLY D. GREEN Examiner Art Unit 2898 /TELLY D GREEN/Primary Examiner, Art Unit 2898 February 25, 2026
Read full office action

Prosecution Timeline

Dec 18, 2023
Application Filed
Feb 25, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
85%
With Interview (+3.7%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 1280 resolved cases by this examiner. Grant probability derived from career allow rate.

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