DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 18 recites the limitation "the base coat layer" in line 3. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner has taken this to be “a base coat layer”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 14-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ono et al. (Ono) (US 2018/0277614 A1).
In regards to claim 1, Ono (Figs. 1-4, 10, 13 and associated text) discloses a display device (Fig. 1) comprising: a substrate (item 402); and a thin film transistor layer (items 28 plus 30 plus 408 plus 414 plus 422 plus 428 plus 432 plus 800) on the substrate (item 402), the thin film transistor layer (items 28 plus 30 plus 408 plus 414 plus 422 plus 428 plus 432) including, in each subpixel (item 22): a first thin film transistor (item 30) including a first semiconductor layer (item 406) of a polysilicon (paragraph 49); and a second thin film transistor (item 28) including a second semiconductor layer (item 424) of an oxide semiconductor (paragraph 52), wherein the second thin film transistor (item 28) includes: the second semiconductor layer (item 424) on a first interlayer insulating film (item 422) farther away from the substrate (item 402) than is the first semiconductor layer (item 406); a second interlayer insulating film (items 428, 430 or 800) covering the second semiconductor layer (item 424); a terminal electrode (item SD2, CNT2, CNT3, SD2 plus CNT2 or SD2 plus CNT3); and a contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) exposing at least a part of the second semiconductor layer (item 424), a metal layer (item 1000) is provided covering an exposed surface of the second semiconductor layer (item 424) exposed inside the contact hole, and the terminal electrode (item SD2, CNT2, CNT3, SD2 plus CNT2 or SD2 plus CNT3) is electrically connected to the second semiconductor layer (item 424) via the contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) and the metal layer (item 1000).
In regards to claim 14, Ono (Figs. 1-4, 10, 13 and associated text) discloses a method of manufacturing a display device (Fig. 1) including: a substrate (item 402); and a thin film transistor layer (items 28 plus 30 plus 408 plus 414 plus 422 plus 428 plus 432 plus 800) on the substrate (item 402), the thin film transistor layer (items 28 plus 30 plus 408 plus 414 plus 422 plus 428 plus 432 plus 800) including, in each subpixel (item 22): a first thin film transistor (item 30) including a first semiconductor layer (item 406) of a polysilicon (paragraph 49); and a second thin film transistor (item 28) including a second semiconductor layer (item 424) of an oxide semiconductor (paragraph 52), the method comprising: a second semiconductor layer (item 424) formation step of forming the second semiconductor layer (item 424) on a first interlayer insulating film (item 422) farther away from the substrate (item 402) than is the first semiconductor layer (item 406); a second interlayer insulating film formation (items 428, 430 or 800) step of forming a second interlayer insulating film (items 428, 430 or 800) covering the second semiconductor layer (item 424); a contact hole formation step of forming a contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) exposing at least a part of the second semiconductor layer (item 424); a metal layer (item 1000) formation step of forming a metal layer (item 1000) covering an exposed surface of the second semiconductor layer (item 424) exposed inside the contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy), by forming a metal film (item 1000) on the second interlayer insulating film (items 428, 430 or 800) through which the contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) has been formed and subsequently patterning the metal film (item 1000); and a terminal electrode (item SD2, CNT2, CNT3, SD2 plus CNT2 or SD2 plus CNT3) formation step of forming a terminal electrode (item SD2, CNT2, CNT3, SD2 plus CNT2 or SD2 plus CNT3) electrically connected to the second semiconductor layer (item 424) via the contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) and the metal layer (item 1000).
In regards to claim 15, Ono (Figs. 1-4, 10, 13 and associated text and items) discloses wherein in the second thin film transistor (item 28), the second semiconductor layer (items 306, 424) includes: a third conductive region (item 306’ and equivalent regions of 424) and a fourth conductive region (item 306’ and equivalent regions of 424) at a distance from each other; and a second channel region (item ACT, 424 Oxide portion) between the third conductive region (item 306’ and equivalent regions of 424) and the fourth conductive region (item 306’ and equivalent regions of 424), a third interlayer insulating film (item 428) is provided on the second interlayer insulating film (item 422), a second gate electrode (item Gate2) is provided on the third interlayer insulating film (item 428), the second gate electrode (item Gate2) being configured to control conduction between the third conductive region (item 306’ and equivalent regions of 424) and the fourth conductive region (item 306’ and equivalent regions of 424), a fourth (third) interlayer insulating film (item 430) is provided covering the second gate electrode (item Gate2), in the contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) formation step, as the contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy), a third contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) and a fourth contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) are formed reaching the third conductive region (item 306’ and equivalent regions of 424) and the fourth conductive region (item 306’ and equivalent regions of 424) and exposing the third conductive region (item 306’ and equivalent regions of 424) and the fourth conductive region (item 306’ and equivalent regions of 424) respectively, and in the metal layer (item 1000) formation step, as the metal layer (item 1000), a first metal layer (item 1000) and a second metal layer (item 1000) are formed covering exposed surfaces of the third conductive region (item 306’ and equivalent regions of 424) and the fourth conductive region (item 306’ and equivalent regions of 424) exposed inside the third contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) and the fourth contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) respectively, the method further comprising, following the metal layer (item 1000) formation step: a third interlayer insulating film (item 428) formation step of forming a third interlayer insulating film (item 428) on the second interlayer insulating film (item 422); a second gate electrode (item Gate2) formation step of forming the second gate electrode (item Gate2) on the third interlayer insulating film (item 428); a fourth interlayer insulating film (item 430) formation step of forming the fourth interlayer insulating film (item 430) on the second gate electrode (item Gate2); and an upper-portion contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) formation step of forming an upper-portion contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) contiguous to the third contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) and the fourth contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy), wherein in the terminal electrode (item SD2, CNT2, CNT3, SD2 plus CNT2 or SD2 plus CNT3) formation step, which follows the upper-portion contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) formation step, a third terminal electrode (item SD2, CNT2, CNT3, SD2 plus CNT2 or SD2 plus CNT3) and a fourth terminal electrode (item SD2, CNT2, CNT3, SD2 plus CNT2 or SD2 plus CNT3) are formed as the terminal electrode (item SD2, CNT2, CNT3, SD2 plus CNT2 or SD2 plus CNT3) on the fourth interlayer insulating film, the third terminal electrode (item SD2, CNT2, CNT3, SD2 plus CNT2 or SD2 plus CNT3) and the fourth terminal electrode (item SD2, CNT2, CNT3, SD2 plus CNT2 or SD2 plus CNT3) being electrically connected respectively to the third conductive region (item 306’ and equivalent regions of 424) and the fourth conductive region (item 306’ and equivalent regions of 424) via the third contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) and the fourth contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) and also via the first metal layer (item 1000) and the second metal layer (item 1000) respectively.
In regards to claim 16, Ono (Figs. 1-4, 10, 13 and associated text) discloses a method of manufacturing a display device (Fig. 1) including: a substrate (item 402); and a thin film transistor layer (items 28 plus 30 plus 408 plus 414 plus 422 plus 428 plus 432 plus 800) on the substrate (item 402), the thin film transistor layer (items 28 plus 30 plus 408 plus 414 plus 422 plus 428 plus 432 plus 800) including, in each subpixel (item 22): a first thin film transistor (item 30) including a first semiconductor layer (item 406) of a polysilicon (paragraph 49); and a second thin film transistor (item 28) including a second semiconductor layer (item 424) of an oxide semiconductor (paragraph 52), the method comprising: a second semiconductor layer (item 424) formation step of forming the second semiconductor layer (item 424) on a first interlayer insulating film (item 422) farther away from the substrate (item 402) than is the first semiconductor layer (item 406); a second interlayer insulating film formation (items 428, 430 or 800) step of forming a second interlayer insulating film (items 428, 430 or 800) covering the second semiconductor layer (item 424); a contact hole formation step of forming a contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) exposing at least a part of the second semiconductor layer (item 424); a metal layer (item 1000) formation step of forming a metal layer (item 1000) covering an exposed surface of the second semiconductor layer (item 424) exposed inside the contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy), by forming a metal film (item 1000) on the second interlayer insulating film (items 428, 430 or 800) through which the contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) has been formed, subsequently applying a resist onto the metal film (item 1000), exposing the resist to light, and then etching the metal film (item 1000) using as a mask the resist that remains along a rim of a bottom portions of the contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy); and a terminal electrode (item SD2, CNT2, CNT3, SD2 plus CNT2 or SD2 plus CNT3) formation step of forming a terminal electrode (item SD2, CNT2, CNT3, SD2 plus CNT2 or SD2 plus CNT3) electrically connected to the second semiconductor layer (item 424) via the contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) and the metal layer (item 1000).
In regards to claim 17, Ono (Figs. 1-4, 10, 13 and associated text) discloses wherein in the second thin film transistor (item 28), the second semiconductor layer (items 306, 424) includes: a third conductive region (item 306’ and equivalent regions of 424) and a fourth conductive region (item 306’ and equivalent regions of 424) at a distance from each other; and a second channel region (item ACT, 424 Oxide portion) between the third conductive region (item 306’ and equivalent regions of 424) and the fourth conductive region (item 306’ and equivalent regions of 424), a third interlayer insulating film (item 428) is provided on the second interlayer insulating film (item 422), a second gate electrode (item Gate2) is provided on the third interlayer insulating film (item 428), the second gate electrode (item Gate2) being configured to control conduction between the third conductive region (item 306’ and equivalent regions of 424) and the fourth conductive region (item 306’ and equivalent regions of 424), a fourth interlayer insulating film (item 430) is provided covering the second gate electrode (item Gate2), in the contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) formation step, as the contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy), a third contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) and a fourth contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) are formed reaching the third conductive region (item 306’ and equivalent regions of 424) and the fourth conductive region (item 306’ and equivalent regions of 424) and exposing the third conductive region (item 306’ and equivalent regions of 424) and the fourth conductive region (item 306’ and equivalent regions of 424) respectively, and in the metal layer (item 1000) formation step, as the metal layer (item 1000), a first metal layer (item 1000) and a second metal layer (item 1000) are formed covering exposed surfaces of the third conductive region (item 306’ and equivalent regions of 424) and the fourth conductive region (item 306’ and equivalent regions of 424) exposed inside the third contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) and the fourth contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) respectively, the method further comprising, following the metal layer (item 1000) formation step: a third interlayer insulating film (item 428) formation step of forming a third interlayer insulating film (item 428) on the second interlayer insulating film (item 422); a second gate electrode (item Gate2) formation step of forming the second gate electrode (item Gate2) on the third interlayer insulating film (item 428); a fourth interlayer insulating film (item 430) formation step of forming the fourth interlayer insulating film (item 430) on the second gate electrode (item Gate2); and an upper-portion contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) formation step of forming an upper-portion contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) contiguous to the third contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) and the fourth contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy), wherein in the terminal electrode (item SD2, CNT2, CNT3, SD2 plus CNT2 or SD2 plus CNT3) formation step, which follows the upper-portion contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) formation step, a third terminal electrode (item SD2, CNT2, CNT3, SD2 plus CNT2 or SD2 plus CNT3) and a fourth terminal electrode (item SD2, CNT2, CNT3, SD2 plus CNT2 or SD2 plus CNT3) are formed as the terminal electrode (item SD2, CNT2, CNT3, SD2 plus CNT2 or SD2 plus CNT3) on the fourth (third) interlayer insulating film, the third terminal electrode (item SD2, CNT2, CNT3, SD2 plus CNT2 or SD2 plus CNT3) and the fourth terminal electrode (item SD2, CNT2, CNT3, SD2 plus CNT2 or SD2 plus CNT3) being electrically connected respectively to the third conductive region (item 306’ and equivalent regions of 424) and the fourth conductive region (item 306’ and equivalent regions of 424) via the third contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) and the fourth contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) and also via the first metal layer (item 1000) and the second metal layer (item 1000) respectively.
In regards to claim 18, Ono (Figs. 1-4, 10, 13 and associated text) discloses wherein the first thin film transistor (item 30) includes: the first semiconductor layer (item 406) on (the) a base coat film (any of the upper 4 layers of item 402), the first semiconductor layer (item 30) including a first conductive region (item 306’ and equivalent regions of 406) and a second conductive region (item 306’ and equivalent regions of 406) at a distance from each other; a gate insulating film (item 408) covering the first semiconductor layer (item 406); a first gate electrode (item Gate1) on the gate insulating film (item 408), the first gate electrode (item Gate1) being configured to control conduction between the first conductive region (item 306’ and equivalent regions of 406) and the second conductive region (item 306’ and equivalent regions of 406); the first interlayer insulating film (item 412) covering the first gate electrode (item Gate1); and a first terminal electrode (item SD1, CNT1, CNT2, SD1 plus CNT1 or SD1 plus CNT2 or CNT1 plus CNT2) and a second terminal electrode (item SD1, CNT1, CNT2, SD1 plus CNT1 or SD1 plus CNT2 or CNT1 plus CNT2) at a distance from each other, the first terminal electrode (item SD1, CNT1, CNT2, SD1 plus CNT1 or SD1 plus CNT2 or CNT1 plus CNT2)and the second terminal electrode (shown but not labeled, hole that SD1, CNT1 and CNT2 occupy) being electrically connected respectively to the first conductive region (item 306’ and equivalent regions of 406) and the second conductive region (item 306’ and equivalent regions of 406), the method further comprising: a first semiconductor layer (item 306, 406) formation step of forming the first semiconductor layer (item 306, 406) on the base coat film (any of the upper 4 layers of item 402); a gate insulating film (item 408) formation step of forming the gate insulating film (item 408) on the first semiconductor layer (item 306, 406); a first gate electrode (item Gate1) formation step of forming the first gate electrode (item Gate1) on the gate insulating film (item 408); a doping step of forming the first conductive region (item 306’ and equivalent regions of 406), a first channel region (item ACT, middle portion of 406), and a second conductive region (item 306’ and equivalent regions of 406) by doping using the first gate electrode (item Gate1) as a mask; and a first interlayer insulating film (item 412) formation step of forming the first interlayer insulating film (item 412) on the first gate electrode (item Gate1), wherein in the contact hole (shown but not labeled, hole that SD1, CNT1 and CNT2 occupy) formation step, as the contact hole, a first contact hole (shown but not labeled, hole that SD1, CNT1 and CNT2 occupy) and a second contact hole (shown but not labeled, hole that SD1, CNT1 and CNT2 occupy) are formed reaching the first conductive region (item 306’ and equivalent regions of 406) and the second conductive region (item 306’ and equivalent regions of 406) respectively, and in the terminal electrode (item SD1, CNT1, CNT2, SD1 plus CNT1 or SD1 plus CNT2 or CNT1 plus CNT2) formation step, the first terminal electrode (item SD1, CNT1, CNT2, SD1 plus CNT1 or SD1 plus CNT2 or CNT1 plus CNT2) and the second terminal electrode (item SD1, CNT1, CNT2, SD1 plus CNT1 or SD1 plus CNT2 or CNT1 plus CNT2) are formed as the terminal electrode (item SD1, CNT1, CNT2, SD1 plus CNT1 or SD1 plus CNT2 or CNT1 plus CNT2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son et al. (Son) (US 2018/0061920 A1) in view of Ono et al. (Ono) (US 2018/0277614 A1).
In regards to claim 1, Son (Figs. 1, 2, 4A, 5A-5M and associated text) discloses a display device (Fig. 1) comprising: a substrate (item SUB); and a thin film transistor layer (items 10 plus PTL plus 30) on the substrate (item SUB), the thin film transistor layer (items 10 plus PTL plus 30) including, in each subpixel (item PX): a first thin film transistor (item T1) including a first semiconductor layer (item SP1) of a polysilicon (paragraph 46); and a second thin film transistor (item T2) including a second semiconductor layer (item SP2) of an oxide semiconductor (paragraph 57), wherein the second thin film transistor (item T2) includes: the second semiconductor layer (item SP2) on a first interlayer insulating film (item PTL) farther away from the substrate (item SUB) than is the first semiconductor layer (item SP1); a second interlayer insulating film (items 21, 22, 23, or 21 plus 22 plus 23) covering the second semiconductor layer (item SP2); a terminal electrode (item IE2); and a contact hole (items OP2 on the left or right) exposing at least a part of the second semiconductor layer (item SP2), but does not specifically disclose a metal layer is provided covering an exposed surface of the second semiconductor layer exposed inside the contact hole, and the terminal electrode is electrically connected to the second semiconductor layer via the contact hole and the metal layer.
Ono (Figs. 1-4, 10, 13 and associated text) discloses a metal layer (item 1000) is provided covering an exposed surface of the second semiconductor layer (item 424) exposed inside the contact hole, and the terminal electrode (item SD2, CNT2, CNT3, SD2 plus CNT2 or SD2 plus CNT3) is electrically connected to the second semiconductor layer (item 424) via the contact hole (shown but not labeled, hole that SD2, CNT2 and CNT3 occupy) and the metal layer (item 1000).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Ono for the purpose of an electrical connection and preventing over-etching (paragraphs78, 79).
In regards to claim 2, Son (Figs. 1, 2, 4A, 5A-5M and associated text) as modified by Ono (Figs. 1-4, 10, 13 and associated text) discloses wherein the thin film transistor layer (items 10 plus PTL plus 30, Son) includes a capacitor (item CST, Son) in each subpixel, the capacitor includes: a lower conductive layer (items CPE1 or CE1, Son); the first interlayer insulating film (item PTL, Son) covering the lower conductive layer (items CPE1 or CE1, Son); the second interlayer insulating film (items 21, 22, 23, or 21 plus 22 plus 23, Son) on the first interlayer insulating film (item PTL, Son); and an upper conductive layer (items CPE2 or CE-U, Son) provided on the second interlayer insulating film (items 21, 22, 23, or 21 plus 22 plus 23, Son) and overlapping the lower conductive layer (items CPE1 or CE1, Son), and the metal layer (item 1000) is provided in a same layer (item 430, Ono), as the upper conductive layer (items CPE2 or CE-U, Son, item Gate2, Ono), but does not specifically disclose the metal layer is made of the same material as the upper conductive layer.
It would have been obvious to modify the invention to include a metal layer made of the same material as the upper conductive layer, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
In regards to claim 3, Son as modified by Ono (Figs. 1-4, 10, 13 and associated text) discloses wherein the metal layer (item 1000) is made of a metal material containing primary of molybdenum (paragraph 79).
In regards to claim 4, Son (Figs. 1, 2, 4A, 5A-5M and associated text and items) as modified by Ono (Figs. 1-4, 10, 13 and associated text and items) discloses wherein the first thin film transistor (item T1) includes: the first semiconductor layer (item SP1) including a first conductive region (item AR11 or AR13) and a second conductive region (item AR11 or AR13) at a distance from each other; a gate insulating film (item 10) covering the first semiconductor layer (item T1); a first gate electrode (item CE1) on the gate insulating film (item 10), the first gate electrode (item CE1) being configured to control conduction between the first conductive region (item AR11 or AR13) and the second conductive region (item AR11 or AR13); the first interlayer insulating film (item PTL) covering the first gate electrode (item CE1); a first terminal electrode (items OE1 or IE1) and a second terminal electrode (items OE1 or IE1) at a distance from each other; and a first contact hole (item OP1 on left or right) and a second contact hole (item OP1 on left or right) exposing the first conductive region (item AR11 or AR13) and the second conductive region (item AR11 or AR13) respectively, wherein in the second thin film transistor (item T2), the second semiconductor layer (item SP2) includes a third conductive region (item AR21 or AR23) and a fourth conductive region (item AR21 or AR23) at a distance from each other, a third interlayer insulating film (items 21, 22, 23, or 21 plus 22 plus 23) is provided on the second interlayer insulating film (item PTL), a second gate electrode (item CE2) is provided on the third interlayer insulating film (items 21, 22, 23, or 21 plus 22 plus 23), the second gate electrode (item CE2) being configured to control conduction between the third conductive region (item AR21 or AR23) and the fourth conductive region (item AR21 or AR23), a fourth interlayer insulating film (item 30) is provided covering the second gate electrode (item CE2), the terminal electrode includes a third terminal electrode (items IE2 or OE2) and a fourth terminal electrode (items IE2 or OE2) at a distance from each other, the contact hole (items OP2 on the left or right) includes a third contact hole (items OP2 on the left or right) and a fourth contact hole (items OP2 on the left or right) exposing the third conductive region (item AR21 or AR23) and the fourth conductive region (item AR21 or AR23) respectively, the metal layer includes a first metal layer (item 1000, Ono) and a second metal layer (item 1000, Ono) covering exposed surfaces of the third conductive region (item AR21 or AR23, Son, source and drain region not labeled, Ono) and the fourth conductive region (item AR21 or AR23, Son, source an drain region not labeled, Ono) exposed inside the third contact hole (items OP2 on the left or right) and the fourth contact hole (items OP2 on the left or right) respectively, the first terminal electrode (items OE1 or IE1), the second terminal electrode (items OE1 or IE1), the third terminal electrode (items IE2 or OE2), and the fourth terminal electrode (items IE2 or OE2) are provided on the fourth interlayer insulating film (item 30), the first terminal electrode (items OE1 or IE1) and the second terminal electrode (items OE1 or IE1) are electrically connected respectively to the first conductive region (item AR11 or AR13) and the second conductive region (item AR11 or AR13) via the first contact hole (item OP1 on left or right) and the second contact hole (item OP1 on left or right), and the third terminal electrode (items IE2 or OE2) and the fourth terminal electrode (items IE2 or OE2) are electrically connected respectively to the third conductive region (item AR21 or AR23, Son, source and drain region not labeled, Ono) and the fourth conductive region (item AR21 or AR23, Son, source and drain region not labeled, Ono) via the third contact hole (items OP2 on the left or right) and the fourth contact hole (items OP2 on the left or right) and also via the first metal layer (item 1000, Ono) and the second metal layer (item 1000, Ono) respectively.
In regards to claim 5, Son (Figs. 1, 2, 4A, 5A-5M and associated text and items) as modified by Ono (Figs. 1-4, 10, 13 and associated text and items) discloses wherein the third contact hole (items OP2 on the left or right) and the fourth contact hole (items OP2 on the left or right) are formed overlapping the third conductive region (item AR21 or AR23, Son, source and drain region not labeled, Ono) and the fourth conductive region (item AR21 or AR23, Son, source and drain region not labeled, Ono) respectively in a plan view.
In regards to claim 6, Son (Figs. 1, 2, 4A, 5A-5M and associated text and items) as modified by Ono (Figs. 1-4, 10, 13 and associated text and items) discloses wherein the third contact hole (items OP2 on the left or right, Son, contact holes of Ono) and the fourth contact hole (items OP2 on the left or right, Son, contact holes of Ono) are formed through a stack of the second interlayer insulating film (item 428, Ono), the third interlayer insulating film (item 430, Ono), and the fourth interlayer insulating film (item 432, Ono), the exposed surfaces of the third conductive region (item AR21 or AR23, Son, source and drain region not labeled, Ono) and the fourth conductive region (item AR21 or AR23, Son, source and drain region not labeled, Ono) are formed respectively on top faces of the third conductive region (item AR21 or AR23, Son, source and drain region not labeled, Ono) and the fourth conductive region (item AR21 or AR23, Son, source and drain region not labeled, Ono) exposed from bottom portions of the third contact hole (items OP2 on the left or right, Son, contact holes of Ono) and the fourth contact hole (items OP2 on the left or right, Son, contact holes of Ono), and the first metal layer (item 1000) and the second metal layer (item 1000) are provided so as to straddle over a rim of the second interlayer insulating film (item 428, Ono) extending along the third contact hole (items OP2 on the left or right, Son, contact holes of Ono) and the fourth contact hole (items OP2 on the left or right, Son, contact holes of Ono) from the top faces of the third conductive region (item AR21 or AR23, Son, source and drain region not labeled, Ono) and the fourth conductive region (item AR21 or AR23, Son, source and drain region not labeled, Ono) respectively.
In regards to claim 7, Son (Figs. 1, 2, 4A, 5A-5M and associated text and items) as modified by Ono (Figs. 1-4, 10, 13 and associated text and items) discloses wherein the third contact hole (items OP2 on the left or right, Son, contact holes of Ono) and the fourth contact hole (items OP2 on the left or right, Son, contact holes of Ono) are formed through the third conductive region (item AR21 or AR23, Son, source and drain region not labeled, Ono) and the fourth conductive region (item AR21 or AR23, Son, source and drain region not labeled, Ono) respectively, the exposed surfaces of the third conductive region (item AR21 or AR23, Son, source and drain region not labeled, Ono) and the fourth conductive region (item AR21 or AR23, Son, source and drain region not labeled, Ono) are formed respectively surrounding faces of the third conductive region (item AR21 or AR23, Son, source and drain region not labeled, Ono) and the fourth conductive region (item AR21 or AR23, Son, source and drain region not labeled, Ono) exposed from surrounding side faces of the third contact hole (items OP2 on the left or right, Son, contact holes of Ono) and the fourth contact hole (items OP2 on the left or right, Son, contact holes of Ono), and the first metal layer (item 1000) and the second metal layer (item 1000) are provided covering the surrounding faces of the third conductive region (item AR21 or AR23, Son, source and drain region not labeled, Ono) and the fourth conductive region (item AR21 or AR23, Son, source and drain region not labeled, Ono) respectively.
In regards to claim 8, Son (Figs. 1, 2, 4A, 5A-5M and associated text and items) as modified by Ono (Figs. 1-4, 10, 13 and associated text and items) discloses wherein the first metal layer (item 1000, Ono) and the second metal layer (item 1000, Ono) are provided so as to straddle over a rim of the second interlayer insulating film (items 428, 430 or 800, Ono) extending along the third contact hole (items OP2 on the left or right, Son, contact holes of Ono) and the fourth contact hole (items OP2 on the left or right, Son, contact holes of Ono) from bottom portions of the third contact hole (items OP2 on the left or right, Son, contact holes of Ono) and the fourth contact hole (items OP2 on the left or right, Son, contact holes of Ono) respectively.
In regards to claim 9, Son (Figs. 1, 2, 4A, 5A-5M and associated text and items) as modified by Ono (Figs. 1-4, 10, 13 and associated text and items) discloses wherein the first metal layer (item 1000) and the second metal layer (item 1000) are post-patterning film remnants from a metal film (item 1000) provided on the second interlayer insulating film (items 428, 430 or 800, Ono).
In regards to claim 10, Son (Figs. 1, 2, 4A, 5A-5M and associated text and items) as modified by Ono (Figs. 1-4, 10, 13 and associated text and items) discloses wherein the third contact hole items OP2 on the left or right, Son, contact holes of Ono) and the fourth contact hole items OP2 on the left or right, Son, contact holes of Ono) are formed through the gate insulating film (item 428, Ono).
In regards to claim 11, Son (Figs. 1, 2, 4A, 5A-5M and associated text and items) and Ono (Figs. 1-4, 10, 13 and associated text and items) both disclose wherein the thin film transistor layer (items 10 plus PTL plus 30, Son, items 28 plus 30 plus 408 plus 414 plus 422 plus 428 plus 432, Ono) includes a planarization film (item ILD, Son, item 434, Ono) covering the first terminal electrode (items OP1 on the left or right, Son, contact holes of Ono), the second terminal electrode (items OP1 on the left or right, Son, contact holes of Ono), the third terminal electrode (items OP2 on the left or right, Son, contact holes of Ono), and the fourth terminal electrode (items OP2 on the left or right, Son, contact holes of Ono).
Claim(s) 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son et al. (Son) (US 2018/0061920 A1) in view of Ono et al. (Ono) (US 2018/0277614 A1) as applied to claims 1-11 above and further in view of Kim et al. (Kim) (US 2021/0143189 A1).
In regards to claim 12, Son (Figs. 1, 2, 4A, 5A-5M and associated text and items) discloses further comprising: a light-emitting element layer (item OLED) including a plurality of light-emitting elements (item OLED) on the thin film transistor layer (items 10 plus PTL plus 30).
Son as modified by Ono does not specifically disclose a sealing film covering the light-emitting element layer (item OLED).
Kim (Fig. 17 and associated text) discloses a sealing film (item 240) covering the light-emitting element layer (item LE).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Kim for the purpose of protecting the light emitting element from impurities [oxygen, moisture, etc.] (paragraph 140).
In regards to claim 13, Son (Figs. 1, 2, 4A, 5A-5M and associated text and items) discloses wherein the plurality of light-emitting elements (item OLED) are organic electroluminescence elements (paragraph 43).
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ono et al. (Ono) (US 2018/0277614 A1) in view of Son et al. (Son) (US 2018/0061920 A1) in view of Kim et al. (Kim) (US 2021/0143189 A1).
In regards to claim 19, Ono (Figs. 1-4, 10, 13 and associated text) discloses a planarization film (items 432, 434 or 432 plus 434) formation step of forming a planarization film (items 432, 434 or 432 plus 434) covering the terminal electrode (item SD1, SD2, CNT1, CNT2, CNT3, SD2 plus CNT2, SD2 plus CNT3, SD1 plus CNT1 or SD1 plus CNT2), but does not specifically disclose a light-emitting element layer formation step of forming, on the planarization film, a light-emitting element layer including a plurality of light-emitting elements.
Son (Figs. 1, 2, 4A, 5A-5M and associated text and items) discloses a light-emitting element layer (item OLED) formation step of forming, on the planarization film (item ILD), a light-emitting element layer (item OLED) including a plurality of light-emitting elements (items ED1, HCL, EML, ECL, ED2).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Son for the purpose of having a light emitting device.
Ono as modified by Son does not specifically disclose a sealing film formation step of forming a sealing film covering the light-emitting element layer.
Kim (Fig. 17 and associated text) discloses a sealing film (item 240) covering the light-emitting element layer (item LE).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Kim for the purpose of protecting the light emitting element from impurities [oxygen, moisture, etc.] (paragraph 140).
In regards to claim 20, Ono as modified by Son (Figs. 1, 2, 4A, 5A-5M and associated text and items) discloses wherein the plurality of light-emitting elements (item OLED) are organic electroluminescence elements (paragraph 43).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. All prior art listed in the 892 could have been used as primary reference in an obviousness rejection in view of Ono. Examiner notes that the references published in 2024 which share the same assignee/Applicant could be used, but would be excluded at some point during prosecution.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 April 24, 2026
Prosecution Insights