DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3, 6, 7 and 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Golonzka et al. (US 2010/0164002 A1; hereinafter, “Golonzka”, of record) in view of French et al. (US 2002/0109800 A1; hereinafter, “French”, of record) and Stavis et al. (US 2011/0123771 A1; hereinafter, “Stavis”).
Regarding claim 1:
Golonzka discloses a method for forming a floating contact, comprising:
obtaining a substrate (Fig. 1a) having a tunnel oxide (i.e., gate oxide of NMOS 104 in Fig. 1a and [0007]) and a plurality of gates 104/106 [0007]) formed thereon;
depositing, photolithographing 114 (Fig. 1b and [0011]), and etching a salicide block (comprising 105, 110 in Fig. 1a and [0010]) to form the salicide block (comprising 105, 110 in Fig. 1b) on the tunnel oxide, on the plurality of gates, and between adjacent gates;
forming a self-aligned silicide 118 (Fig. 1c and [0013]) at a portion where the salicide block 105/107/110 is not formed;
forming an interlayer dielectric layer 140/142 (Fig. 1g and [0020]) on the plurality of gates, on the salicide block and on the self-aligned silicide;
etching the interlayer dielectric layer 140/142 and the salicide block 105/107/110 by taking the photoresist pattern as an etching mask layer to obtain the floating contact 128 in the interlayer dielectric 140/142 and the silicide block 105/107/110 (Fig. 1g), wherein during said etching to obtain the floating contact, the photoresist strip is consumed up (i.e., in [0020] an opening is formed for contacts 128 but not shown; furthermore, in order to form openings for contacts 128, the entire structure, comprising the ILD 140/142 and the salicide block 105/107/110, is etched to form the openings, i.e., the current claim does not require any portion of the salicide block 105/107/110 to be removed by the etching; lastly, in Fig. 1g, the contacts 128 a “floating” above the substrate 102, accordingly, a floating contact 128 is obtained).
Golonzka does not disclose details of how the openings for contacts 128 are formed; accordingly, Golonzka does not disclose the strikethrough limitations above. However, it is noted that contact holes are commonly formed by photolithography processes that are very well known in the art, and the strikethrough limitations are considered to be an elaborate description for a well-known process of forming and patterning a positive photoresist.
French is cited to show it was very well known in the art to use a positive photoresist layer [0033], patterning the photoresist layer comprising steps including exposing the photoresist layer through a photomask with opaque and transparent areas and developing to leave a reduced thickness pattern (i.e., partial removal), wherein the positive photoresist layer is used to form contacts [0068].
Stavis is also cited to show an example of using a positive photoresist by coating a photoresist 40 (Fig. 2 and [0021-0022]) on a layer 42, exposing the photoresist through a contact hole photomask (“22” in Fig. 1), and followed by developing to obtain a photoresist pattern (“24” in Fig. 1 and “41” in Fig. 2, [0021]) wherein the contact hole photomask includes a floating contact pattern (e.g., the pattern formed by “41” in Fig. 2), the floating contact pattern comprising a photoresist retention region (e.g., all regions containing “40” in the pattern “41” shown at the top of Fig. 2) and a remaining region (the region where portions of “40” were removed at the top of Fig. 2) other than the photoresist retention region, the photoresist retention region having a light transmittance opposite to that of the remaining region (e.g., in the center of Fig. 2, the photoresist region “40” remaining at the sides of the Fig. have a light transmittance opposite that of the portions corresponding to “44/44b”, i.e., there is no more photoresist in regions “44/44b” to block light transmittance), and wherein the photoresist pattern in the remaining region are removed during developing (“24” in Fig. 1), and the photoresist pattern in the photoresist retention region are partially removed during developing by controlling an exposure condition during exposure to form a photoresist strip (i.e., the thick portions of “40” at the left and right ends of Fig. 2) in the photoresist retention region. Furthermore, Stavis discloses (at the bottom of Fig. 2 and [0022]) the photoresist strip (“40”) is consumed up during an etching step.
Because Golonzka is silent with respect to details for forming the opening for contacts 128, one of ordinary skill in the art would have incorporated any well-known process in the art; accordingly, it would have been obvious to one of ordinary skill in the art to specifically incorporate a photolithographic process comprising a positive photoresist because French and Stavis show such processes were very well known and suitable for forming contacts.
Regarding claims 2, 3, 6, 7 and 11-14:
re claim 2, French discloses the photoresist is a positive photoresist {0033, 0068], the
photoresist retention region is an opaque region, and the remaining region is a transparent region; and the partially removing the photoresist pattern in the photoresist retention region during developing by controlling the exposure condition comprises overexposing the photoresist ([0033], i.e., overexposing a positive photoresist is common in the art, e.g., to enhance lift-off; accordingly, this claim is deemed obvious over Golonzka in view of French and Stavis);
re claim 3, the photoresist retention region can be a chosen portion of the mask remaining after development; accordingly, an appropriately sized region can be readily chosen to be the photoresist retention region that accounts for 30% to 40% of a width of the entire floating contact portion (i.e., this claim is deemed obvious over Golonzka in view of French and Stavis by choosing a suitable region of the entire photoresist pattern/retention region);
re claims 6 and 7, Golonzka (in view of French and Stavis) discloses the formed salicide block 105/107/110 (Fig. 1b and [0008]) comprises a first oxide layer 107; however, Golonzka (in view of French and Stavis) does not specify any ranges in thickness for the first oxide layer or the tunnel oxide layer; accordingly, Golonzka (in view of French and Stavis) does not disclose the currently recited ranges. However, the current claims are deemed obvious because the prior art discloses the general conditions of the claimed invention, and given the prior art, one of ordinary skill in the art would have been able to determine optimum or workable ranges in thickness for the first oxide layer and the tunnel oxide layer without extensive experimentation. In other words, the currently claimed ranges (400 Å to 600 Å and 1000 Å to 1200 Å) are considered to be optimum or workable ranges for some specific design requirement, e.g., for a particular type of semiconductor device, and given the specific design requirement, one of ordinary skill in the art would have been able find an optimum or workable range. Note it has been held that where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation (MPEP 2144.05). In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955);
re claim 11, when forming the openings for floating contacts 128 (Golonzka, Fig. 1g) are completed, an end point is readily detected; accordingly, this claim is deemed obvious over Golonzka (in view of French and Stavis);
re claim 12, Golonzka discloses after the obtaining the floating contact, filling the floating contact with a conductive material (to form “128”, Fig. 1g and [0020]);
re claim 13, the limitations in this claim are considered to be an elaborate description of a conventional process of patterning a photoresist layer including exposure and development, i.e., Stavis discloses forming a photoresist strip by controlling the exposure condition (e.g., grayscale radiation, Fig. 1, “22” and Fig. 2, top, “46/48/44”), a portion of a photoresist region in partially dissolved by a developing solution, forming a photoresist strip in a middle of the photoresist region that is dissolved by the developing solution; therefore, this claim is deemed obvious over Golonzka (in view of French); and
re claim 14, Golonzka discloses each of the plurality of gates 104/106 is a gate of a logic device (NMOS or PMOS, Fig. 1b) and/or a memory.
Therefore, Golonka (in view of French and Stavis) render claims 2, 3, 6, 7 and 11-14 obvious.
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Golonzka (in view of French and Stavis) as applied to claim 1 above, and further in view of Huang et al. (US 2009/0001462 A1; hereinafter, “Huang”, of record).
Regarding claim 4:
Golonzka (in view of French and Stavis) does not disclose a laterally diffused metal oxide semiconductor field effect transistor (LDMOS).
Huang is cited to show LDMOS device (Fig.3G and [0037]) were very well known in the art, and such devices comprise source regions 319 and drain regions 317.
It would have been obvious to one of ordinary skill in the art to specifically incorporate a floating contact, as disclosed by Golonzka (in view of French and Stavis), into an LDMOS because Huang shows such devices were very well known and common in the art. Furthermore, one of ordinary skill in the art would have been able to incorporate the floating contact of Golonzka (in view of French and Stavis) without extensive experimentation because it appears from the current specification and drawings that such contacts are easily incorporated into well-known semiconductor devices, especially because the current drawings merely depict a substrate 10 with four layers 20/30/40 thereon, and a pattern photoresist layer used to form an opening 11 (i.e., a floating contact). In other words, based on the current specification and drawings, it appears one of ordinary skill in the art is presumed to readily understand where and how a floating contact would be incorporated into semiconductor devices in general.
Regarding claim 5:
The photoresist retention region can be a chosen portion of the mask remaining after development; accordingly, an appropriately sized region can be readily chosen to be the photoresist retention region that accounts for 30% to 40% of a width of the entire floating contact portion (i.e., this claim is deemed obvious over Golonzka in view of French, Stavis and Huang by choosing a suitable region of the entire photoresist pattern/retention region);
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Golonzka (in view of French and Stavis) as applied to claim 1 above, and further in view of Nishida et al. (US 2003/0151098 A1; hereinafter, “Nishida”, of record).
Golonzka (in view of French and Stavis) discloses each of the plurality of gates 104/106 (see Golonzka, Fig. 1b and [0007]) comprises a gate oxide layer (inherent to the NMOS and PMOS in Fig. 1b) and a [metal] gate on the gate oxide layer, and a spacer 108 [0009] on both sides of each of the plurality of gates 104/106 is formed on the substrate obtained in the obtaining the substrate.
Golonzka (in view of French and Stavis) does not disclose a polysilicon gate. However, Nishida is cited to show it was very well known in the art that a semiconductor device, similar to that of Golonzka, can be formed with polysilicon gates 11/21 (e.g., PS1/PS2 in Figs. 1-4 and [006]) or with a metal gate [0035-0036] depending on, e.g., a desired work function [0124].
It would have been obvious to one of ordinary skill in the art to modify Golonzka (in view of French and Stavis) by incorporating metal gates because Nishida shows/teaches such a modification would provide means to modify a work function of the gate.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Golonzka (in view of French and Stavis) as applied to claim 1 above, and further in view of Kim (US 2010/0090310 A1, of record).
Golonzka (in view of French and Stavis) does not disclose the method is applied to a Bipolar-CMOS-DMOS (BCD) process.
Kim is cited to show a BCD process was very well known in the art.
It would have been obvious to one of ordinary skill in the art to specifically apply the process disclosed by Golonzka (in view of French and Stavis) to a BCD process because Kim shows such a process were very well known in the art. Furthermore, one of ordinary skill in the art would have been able to incorporate the process disclose by Golonzka (in view of French and Stavis) without extensive experimentation because it appears from the current specification and drawings that such a process is easily incorporated into well-known semiconductor processes, especially because the current drawings merely depict a substrate 10 with four layers 20/30/40 thereon, and a process of forming a contact opening in the four layers. In other words, based on the current specification and drawings, it appears one of ordinary skill in the art is presumed to readily understand how a process as recited in claim 1 (or in Golonzka in view of French and Stavis) would be incorporated into semiconductor devices in general.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Golonzka (in view of French and Stavis) as applied to claim 1 above, and further in view of Pidin (US 2009/0108463 A1, of record).
Golonzka (in view of French and Stavis) does not disclose any etching gases used to etch the interlayer dielectric layer.
Pidin is cited to show it was very well known in the art to use an etching gas for the dry etching comprising C4F₈ and O₂ (Fig. 7B and [0104]).
Because Golonzka (in view of French and Stavis) is silent with regard to any etching gases, it would have been obvious to one of ordinary skill in the art to specifically incorporate C4F₈ and O₂ because Pidin shows such etching gases were well known to use when etching an interlayer dielectric layer similar to that in Golonzka.
Remarks
The objection to the specification is withdrawn in view of applicant’s clarification that “tunnel oxide” is interpreted as “oxide”.
Applicant’s remarks have been carefully reviewed and considered, but they are moot in view of the new grounds of rejections. Specifically, Stavis is cited to show it was well known in the art to partially remove a photoresist by controlling exposure conditions to form a photoresist strip; and because Golonzka forms a floating contact using a positive photoresist, claim 1 is deemed obvious over Golonzka (in view of French and Stavis), i.e., Since Golonzka is silent as to the details of a photolithography process used for forming the floating contact, it would have been obvious to one of ordinary skill in the art to incorporate any well-known photolithography process, such as that discloses by French and/or Stavis.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM).
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/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
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