Prosecution Insights
Last updated: May 29, 2026
Application No. 18/572,949

SEMICONDUCTOR ELEMENT AND PRODUCTION METHOD FOR SEMICONDUCTOR ELEMENT

Non-Final OA §102§103
Filed
Dec 21, 2023
Priority
Jun 25, 2021 — JP 2021-105412 +1 more
Examiner
FERNANDES, ERROL V
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
UNIVERSITY PUBLIC CORPORATION OSAKA
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
682 granted / 801 resolved
+17.1% vs TC avg
Moderate +12% lift
Without
With
+11.5%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
15 currently pending
Career history
817
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
85.0%
+45.0% vs TC avg
§102
12.5%
-27.5% vs TC avg
§112
2.3%
-37.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 801 resolved cases

Office Action

§102 §103
DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mitsuharu JP 2017-135171 A (see attached English Translation). Regarding claim 1, Mitsuharu discloses: A semiconductor element (Figs. 6-7 in view of 4-5) comprising: a gallium oxide layer (41; para 0026 gallium oxide); a single-crystal silicon carbide layer (21; para 0019 silicon carbide) formed at one principal surface side of the gallium oxide layer; and a first electrode formed at the one principal surface side of the gallium oxide layer and controls current flowing inside the gallium oxide layer (para 0030; back surface electrode formed on the back of the semiconductor substrate 6 opposite 41 using nickel or the like). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4, 5 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mitsuharu in view of Liang et al. Fabrication and Characterization of Ga2O3/3C-SiC Bonding Interface, Proceedings of the 67th Spring Meeting of the Japan Society of Applied Physics (2020, Sophia University, Yotsuya Campus) (see attached English Translation). Regarding claims 4 and 5, Mitsuharu discloses: (claim 4) further comprising: a conjugation layer formed at a boundary face between the gallium oxide layer and the silicon carbide layer; and (claim 5) wherein the conjugation layer includes a first amorphous layer consisting of gallium oxide formed on the one principal surface of the gallium oxide layer, and a second amorphous layer consisting of silicon carbide formed between the first amorphous layer and the silicon carbide layer. Liang discloses a publication from a similar field of endeavor in which: (claim 4) further comprising: a conjugation layer formed at a boundary face between the gallium oxide layer and the silicon carbide layer; and (claim 5) wherein the conjugation layer includes a first amorphous layer consisting of gallium oxide formed on the one principal surface of the gallium oxide layer, and a second amorphous layer consisting of silicon carbide formed between the first amorphous layer and the silicon carbide layer (see left column and lines 19-26, crystal defect layer observed … the thickness of the crystal defect layer in SiC and Ga2O3 each approximately 1 nm). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the bonding technique resulting in a intermediate conjugation layer of Liang for providing the SiC layer on Ga2O3 stack of Mitsuharu as an alternative technique for determining the similar structure with reduced defects at the interface thereby alleviating functional performance and reliability concerns related to Ga2O3 thin film layers. Regarding claim 12, Mitsuhau discloses: A method for manufacturing a semiconductor element (Figs. 6-7 in view of 4-5) comprising: a step of growing one principal surface of a gallium oxide layer (41; para 0026 gallium oxide) and a single-crystal silicon carbide layer (21; para 0019 silicon carbide) (as in Fig. 5); and a step of forming a first electrode at the one principal surface side of the gallium oxide layer for controlling current flowing in the gallium oxide layer (para 0030; back surface electrode formed on the back of the semiconductor substrate 6 opposite 41 using nickel or the like). Mitsuharu does not disclose: using a step of joining for determining the gallium oxide layer and a single-crystal silicon carbide layer structure. Liang discloses a publication from a similar field of endeavor in which: using a step of joining for determining the gallium oxide layer and a single-crystal silicon carbide layer structure (see left column and lines 7-9, surface activated bonding using Ga2O3 with SiC). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the bonding technique of Liang for providing the SiC layer on Ga2O3 stack of Mitsuharu as an alternative technique for determining the similar structure with reduced defects at the interface thereby alleviating functional performance and reliability concerns related to Ga2O3 thin film layers. Claims 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mitsuharu/Liang in further view of Arima et al. US 2021/0343879 A1. Regarding claims 7 and 8, Mitsuharu/Liang do not disclose: (claim 7) wherein the gallium oxide layer includes a first gallium oxide layer, and a second gallium oxide layer formed on one principal surface of the first gallium oxide layer and having a lower conductivity than the first gallium oxide layer; and (claim 8) wherein the conjugation layer is formed in a first region of one principal surface of the second gallium oxide layer, and the first electrode is formed in a second region of the one principal surface of the second gallium oxide layer, which is different from the first region. Arima discloses a publication from a similar field of endeavor in which: (claim 7) wherein the gallium oxide layer includes a first gallium oxide layer (20), and a second gallium oxide layer (30) formed on one principal surface of the first gallium oxide layer and having a lower conductivity than the first gallium oxide layer; and (claim 8) wherein the conjugation layer (70) is formed in a first region of one principal surface of the second gallium oxide layer, and the first electrode (40) is formed in a second region of the one principal surface of the second gallium oxide layer, which is different from the first region (Figs. 1 and 2). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the further structural features of Arima including the first/second gallium oxide layers, the conjugation layer and the first/second electrodes to form a similar Schottky barrier diode as taught by Mitsuharu/Liang being less liable to cause dielectric breakdown due to concentration of an electric field. Claim 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mitsuharu JP 2017-135171 A (see attached English Translation) in view of Arima et al. US 2021/0343879 A1. Regarding claim 11, Mitsuharu does not disclose: wherein the first electrode is in Schottky contact with the gallium oxide layer, and the semiconductor element further comprising: a second electrode in ohmic contact with other principal surface of the gallium oxide layer. Arima discloses a publication from a similar field of endeavor in which: wherein the first electrode (40) is in Schottky contact with the gallium oxide layer, and the semiconductor element further comprising: a second electrode (50) in ohmic contact with other principal surface of the gallium oxide layer (Figs. 1 and 2). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the first and second electrodes of Arima to form a similar Schottky barrier diode as taught by Mitsuharu being less liable to cause dielectric breakdown due to concentration of an electric field. Allowable Subject Matter Claims 2, 3, 6, 9 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or clearly suggest the limitations of claim 2 stating “wherein the silicon carbide layer has a 3C type crystal structure, a plane orientation of a principal surface of the silicon carbide layer at the gallium oxide layer side is (111), (100), or (110), an off angle of the principal surface of the silicon carbide layer at the gallium oxide layer side is between 0° and 10°, and the silicon carbide layer satisfies at least one of the conditions of a half width of a X-ray rocking curve of the surface orientation of the principal surface of the silicon carbide layer at the gallium oxide layer side is greater than 0 and equal to or less than 2000 arcsec, and a full width at half maximum of the misorientation distribution of the principal surface of the silicon carbide layer at the gallium oxide layer side determined by an electron beam backscatter diffraction method is greater than 0 and equal to or less than 2000 arcsec”; of claim 3 stating “wherein the silicon carbide layer has a crystal structure of a hexagonal crystal, the surface orientation of the principal surface of the silicon carbide layer at the gallium oxide layer side is (0001), an off angle of the principal surface of the silicon carbide layer at the gallium oxide layer side is between 0° and 10°, and the silicon carbide layer satisfies at least one of the conditions of a half width of a X-ray rocking curve of the surface orientation of the principal surface of the silicon carbide layer at the gallium oxide layer side is greater than 0 and equal to or less than 2000 arcsec, and a full width at half maximum of the misorientation distribution of the principal surface of the silicon carbide layer at the gallium oxide layer side determined by an electron beam backscatter diffraction method is greater than 0 and equal to or less than 2000 arcsec”; of claim 6 stating “wherein the conjugation layer includes silicon oxide”; and of claim 9 stating “wherein the second gallium oxide layer is formed in a third region of the one principal surface of the first gallium oxide layer, the conjugation layer is formed in a fourth region of the one principal surface of the first gallium oxide layer, which is different from the third region, and the first electrode is formed on one principal surface of the second gallium oxide layer”. In light of these limitations, the prior art fails to anticipate or make obvious the claimed invention. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERROL V FERNANDES/Primary Examiner, AU 2893
Read full office action

Prosecution Timeline

Dec 21, 2023
Application Filed
Apr 07, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
97%
With Interview (+11.5%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 801 resolved cases by this examiner. Grant probability derived from career allowance rate.

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