Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/26/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamazaki et al. (US 2017/0033111).
As for claim 1, Yamazaki et al. disclose in Fig.1a-1b or 14a-14b and the related text a transistor comprising:
a first gate electrode 102a;
a first insulator 105/103 over the first gate electrode;
a second insulator 103/104 over the first insulator;
a third insulator (middle portion of 106a), a fourth insulator (left portion of 106a), and a fifth insulator (right portion of 106a) over the second insulator;
an oxide semiconductor 106b over the third insulator, the fourth insulator, and the fifth insulator;
a first conductor 108a and a second conductor 108b over the oxide
semiconductor;
a sixth insulator (lower portion of 117) over the first conductor and the second conductor and the third conductor;
a seventh insulator (upper portion of 117) over the sixth insulator; and
a second gate electrode 114a embedded in an opening of the sixth insulator and an opening of the seventh insulator (Fig. 1A-1B)
wherein the sixth insulator (lower portion of 117) is in (thermally/electrically) contact with a top surface of the first insulator, a side surface of the oxide semiconductor, a side surface and a top surface of the first conductor, and a side surface and a top surface of the second conductor (Fig. 1B),
wherein the second gate electrode 114a overlaps with the third insulator is positioned to overlap with a first region of the oxide semiconductor therebetween (Fig. 1B),
wherein the second conductor 108a overlaps with the fourth insulator with a second region of the oxide semiconductor therebetween (Fig. 1B)
wherein the second conductor 108b overlaps with the fifth insulator with a third region of the oxide semiconductor therebetween (Fig. 1B), and
wherein a top surface of the third insulator (middle portion of 106a) is level or substantially level with a top surface of the fourth insulator (left portion of 106a), and a top surface of the fifth insulator (right portion of 106a) (Fig. 1B).
As for claim 2, Yamazaki et al. disclose the transistor according to claim 1, further comprising:
an eighth insulator 106ca over the oxide semiconductor;
a ninth insulator 112a over the eighth insulator; and
a tenth insulator 116 over the seventh insulator, the eighth insulator, the ninth insulator and the second gate electrode (Fig. 1B),
wherein in a cross section in a channel width direction of the transistor, the eighth
insulator is in (thermally/electrically) contact with the each of the third insulator, the oxide semiconductor, and the seventh insulator (Fig. 1B),
wherein a thickness of the eighth insulator 106ca is smaller than a thickness of the ninth insulator 112a (Fig. 1B), and wherein a top surface of the second gate electrode 114a is level or substantially level with a top surface of the seventh insulator (Fig. 1B).
As for claim 3, Yamazaki et al. disclose the transistor according to claim 2, wherein the top surface of the second gate electrode 114A is level or substantially level with an uppermost portion of the eighth insulator 106ca and an uppermost portion of the ninth insulator 112a (Fig. 1B).
As for claim 4, Yamazaki et al. disclose the transistor according to claim 2, wherein the eighth insulator comprises aluminum and oxygen [0143], and the thickness of the eighth insulator is greater than or equal to 1.0 nm and less than or equal to 3.0 nm [0155].
As for claim 5, Yamazaki et al. disclose the transistor according to claim 1, wherein each of the first insulator 103 [0187] and the sixth insulator (lower portion of 117a) comprises silicon and nitrogen [0205], wherein the second insulator 104 comprises aluminum and oxygen [0189], and wherein each of the third insulator and the seventh insulator (upper portion of 117a) comprises silicon and oxygen [0205].
As for claim 6, Yamazaki et al. disclose the transistor according to claim 2,
further comprising:
an eleventh insulator 116 over the tenth insulator (Fig. 14B),
wherein the eleventh insulator is in (thermally/electrically) contact with the top surface of the first insulator, a side surface of the sixth insulator, a side surface of the seventh insulator, and a side surface and a top surface of the tenth insulator (Fig. 14B), and
wherein the eleventh insulator comprises silicon and nitrogen [0211].
As for claim 7, Yamazaki et al. disclose in Fig. 14a-14b and the related text a transistor comprising:
a first insulator 103;
a second insulator 104 over the first insulator;
a third insulator (middle portion of 106a), a fourth insulator (left portion of 106a), and a fifth insulator (right portion of 106a) over the second insulator;
an oxide semiconductor 106b over the third insulator, the fourth insulator, and the fifth insulator;
a first conductor 108a and a second conductor 108b over the oxide semiconductor;
a sixth insulator (lower portion of 117a) over the first conductor and the second conductor (Fig. 14B);
a seventh insulator (upper portion of 117a) over the sixth insulator (Fig. 14B);
an eighth insulator 106ca/112a over the oxide semiconductor (Fig. 14B);
a gate electrode 114a embedded in an opening of the sixth insulator and an opening of the seventh insulator (Fig. 14B); and
a ninth insulator 117b over the seventh insulator, the eighth insulator, and the gate electrode (Fig. 14B),
wherein the sixth insulator (lower portion of 117a) is in (thermally/electrically) contact with a top surface of the first insulator, a side surface of the oxide semiconductor, a side surface and a top surface of the first conductor, and a side surface and a top surface of the second conductor (Fig. 14B), wherein the gate electrode 114a overlaps with the third insulator with a first region of the oxide semiconductor therebetween (Fig. 14B),
wherein the first conductor 108a overlaps with the fourth insulator with a second region of the oxide semiconductor therebetween (Fig. 14B),
wherein the second conductor 108b overlaps with the fifth insulator with a third region of the oxide semiconductor therebetween (Fig. 14B),
wherein in a cross section in a channel width direction of the transistor, the eighth
insulator 106ca/112a is in (thermally/electrically) contact with each of the third insulator, the oxide semiconductor, and the seventh insulator (Fig. 14B), and
wherein a top surface of the third insulator (middle portion of 106a) is level or substantially level with a top surface of the fourth insulator (left portion of 106a), and a top surface of the fifth insulator (right portion of 106a).
As for claim 8, Yamazaki et al. disclose the transistor according to claim 7, wherein a top surface
of the gate electrode 114a is level or substantially level with a top surface of the
seventh insulator (Fig. 14B).
As for claim 9, Yamazaki et al. disclose the transistor according to claim 8, wherein the top surface of the gate electrode 114a is level or substantially level with an uppermost portion of the eighth insulator (Fig. 14B).
As for claim 10, Yamazaki et al. disclose the transistor according to claim 7, wherein each of the first insulator 103 [0187] and the sixth insulator (lower portion of 117a) comprises silicon and nitrogen [0205], wherein the second insulator 104 comprises aluminum and oxygen [0189], and wherein each of the third insulator and the seventh insulator (upper portion of 117a) and the eighth insulator 112a comprises silicon and oxygen [0205].
As for claim 11, Yamazaki et al. disclose the transistor according to claim 7, further comprising:
a tenth insulator 116 over the ninth insulator,
wherein the tenth insulator is in (thermally/electrically) contact with the top surface of the first insulator, the side surface of the sixth insulator, the side surface of the seventh insulator, and a side surface, and a top surface of the ninth insulator (Fig. 14B), and
wherein the tenth insulator 116 comprises silicon and nitrogen [0211].
As for claim 12, Yamazaki et al. disclose the transistor according to claim 7,
wherein each of the oxide semiconductor, the fourth insulator, and the fifth insulator
comprises indium, gallium, zinc, and oxygen [0159], and wherein an atomic ratio of gallium to indium in the fourth insulator is higher than an atomic ratio of gallium to indium in the oxide semiconductor [0159].
As for claim 13, Yamazaki et al. disclose the transistor according to claim 7, wherein the oxide semiconductor comprises a region with a hydrogen concentration lower than 1 X 10¹⁹ atoms/cm³ when the oxide semiconductor is measured by secondary ion mass spectrometry [0159].
Conclusion
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811