DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) submitted on 12/27/2023 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1- 8 and 11 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Yamaguchi (US 2018/0294286) . Regarding claim 1 , Yamaguchi discloses, in at least figure s 3, 10-11, 19-21, and related text, a display device comprising: a base substrate layer (100, [41], [71]); and a thin film transistor layer (layer of TFTs of TFT substrate 100, [36], [38], [41], [71]) on the base substrate layer (100, [41], [71]), the thin film transistor layer (layer of TFTs of TFT substrate 100, [36], [38], [41], [71]) including, in each of a plurality of subpixels ([38]): a first thin film transistor (LTPS TFT, [4], [41]) including a first semiconductor layer (102, [43]) of a polysilicon ([4]) ; and a second thin film transistor (TAOS TFT, [6], [41]) including a second semiconductor layer (110, [42]) of an oxide semiconductor ([6]) , wherein the first thin film transistor (LTPS TFT, [4], [41]) includes: the first semiconductor layer (102, [43]) including a first conductive region (source/drain 102 in left side of 1021, [47], figure 3) and a second conductive region (source/drain 102 in right side of 1021, [47], figure 3) at a distance from each other; a first gate insulating film (103, [46]) on the first semiconductor layer (102, [43]) ; a first gate electrode (104, [46]) on the first gate insulating film (103, [46]) , the first gate electrode (104, [46]) being configured to control conduction between the first conductive region (source/drain 102 in left side of 1021, [47], figure 3) and the second conductive region (source/drain 102 in right side of 1021, [47], figure 3) ; an interlayer insulating film (105, [42]) covering the first gate electrode (104, [46]) ; and a first terminal electrode (106, [50]) and a second terminal electrode (107, [50]) on the interlayer insulating film (105, [42]) at a distance from each other, the first terminal electrode (106, [50]) and the second terminal electrode (107, [50]) being electrically connected respectively to the first conductive region (source/drain 102 in left side of 1021, [47], figure 3) and the second conductive region (source/drain 102 in right side of 1021, [47], figure 3) via a first contact hole (108, [50]) and a second contact hole (108, [50]) formed at least through the interlayer insulating film (105, [42]) , the second thin film transistor (TAOS TFT, [6], [41]) includes: the second semiconductor layer (110, [42], [46]) including a third conductive region (source/drain 110 in left side of 111, [47], figure 3) and a fourth conductive region (source/drain 110 in right side of 111, [47], figure 3) at a distance from each other; a first conductive layer (112, [42]) and a second conductive layer (113, [42]) on a base substrate layer side of the third conductive region (source/drain 110 in left side of 111, [47], figure 3) and the fourth conductive region (source/drain 110 in right side of 111, [47], figure 3) respectively, the first conductive layer (112, [42]) and the second conductive layer (113, [42]) being made of a same material ([42]) , and provided in a same layer, as the first semiconductor layer (102, [43]) ; a second gate insulating film (103, [46]) on the second semiconductor layer (110, [42], [46]) ; a second gate electrode (104, [46]) on the second gate insulating film (103, [46]) , the second gate electrode (104, [46]) being configured to control conduction between the third conductive region (source/drain 110 in left side of 111, [47], figure 3) and the fourth conductive region (source/drain 110 in right side of 111, [47], figure 3) ; the interlayer insulating film (105, [42]) covering the second gate electrode (104, [46]) ; and a third terminal electrode (106, [50]) and a fourth terminal electrode (107, [50]) on the interlayer insulating film (105, [42]) at a distance from each other, the third terminal electrode (106, [50]) and the fourth terminal electrode (107, [50]) being electrically connected respectively to the first conductive layer (112, [42]) and the second conductive layer (113, [42]) via a third contact hole (108, [50]) and a fourth contact hole (108, [50]) formed at least through the interlayer insulating film (105, [42]) , and the second gate insulating film (103, [46]) is made of a same material, and provided in a same layer, as the first gate insulating film (103, [46]) (figure 3) . Regarding claim 2 , Yamaguchi discloses the display device according to claim 1 as described above. Yamaguchi further discloses, in at least figure s 3, 10-11, 19-21, and related text, the first gate insulating film (103, [46]) and the second gate insulating film (103, [46]) are an integrally formed gate insulating film (103, [46]) (figure 3). Regarding claim 3 , Yamaguchi discloses the display device according to claim 2 as described above. Yamaguchi further discloses, in at least figure s 3, 10-11, 19-21, and related text, the first contact hole (108, [50]), the second contact hole (108, [50]), the third contact hole (108, [50]), and the fourth contact hole (108, [50]) are formed through the gate insulating film (103, [46]) and the interlayer insulating film (105, [42]) (figure 3). Regarding claim 4 , Yamaguchi discloses the display device according to claim 1 as described above. Yamaguchi further discloses, in at least figure s 3, 10-11, 19-21, and related text, the first gate insulating film (103, [46]) is insularly provided overlapping the first gate electrode (104, [46]), and the second gate insulating film (103, [46]) is insularly provided overlapping the second gate electrode (104, [46]) (figure 3). Regarding claim 5 , Yamaguchi discloses the display device according to claim 1 as described above. Yamaguchi further discloses, in at least figure s 3, 10-11, 19-21, and related text, the first gate insulating film (103, [46]) and the second gate insulating film (103, [46]) have at least a base substrate layer side including a silicon oxide film ([46]) (figure). Regarding claim 6 , Yamaguchi discloses the display device according to claim 1 as described above. Yamaguchi further discloses, in at least figure s 3, 10-11, 19-21, and related text , the first conductive region (source/drain 102 in left side of 1021, [47], figure 3), the second conductive region (source/drain 102 in right side of 1021, [47], figure 3), the first conductive layer (112, [42]), and the second conductive layer (113, [42]) are doped with phosphorus ([47]) (figure 10). Regarding claim 7 , Yamaguchi discloses the display device according to claim 1 as described above. Yamaguchi further discloses, in at least figure s 3, 10-11, 19-21, and related text , the first conductive region (source/drain 102 in left side of 1021, [47], figure 3) and the second conductive region (source/drain 102 in right side of 1021, [47], figure 3) are doped with boron ( [24], figure 11), and the first conductive layer (112, [42]) and the second conductive layer (113, [42]) are doped with phosphorus ([47], figure 10). Regarding claim 8 , Yamaguchi discloses the display device according to claim 1 as described above. Yamaguchi further discloses, in at least figure s 3, 10-11, 19-21, and related text , the second thin film transistor (TAOS TFT, [6], [41]) is a N-type thin film transistor (n-MOS TAOS, [47]) in which the first conductive layer (112, [42]) and the second conductive layer (113, [42]) are doped with phosphorus ([47], figure 10), and the first thin film transistor (LTPS TFT, [4], [41]) includes: a N-type thin film transistor (n-MOS LTPS, [47]) in which the first conductive region (source/drain 102 in left side of 1021, [47], figure 3) and the second conductive region (source/drain 102 in right side of 1021, [47], figure 3) are doped with phosphorus ([47], figure 10); and a P-type thin film transistor (p-MOS LTPS, [47]) in which the first conductive region (source/drain 102 in left side of 1021, [47], figure 3) and the second conductive region (source/drain 102 in right side of 1021, [47], figure 3) are doped with boron ([24], figure 11). Regarding claim 11 , Yamaguchi discloses, in at least figure s 3-14, 1 8 -21, and related text, a method of manufacturing a display device including: a base substrate layer (100, [41], [71]); and a thin film transistor layer (layer of TFTs of TFT substrate 100, [36], [38], [41], [71]) on the base substrate layer (100, [41], [71]), the thin film transistor layer (layer of TFTs of TFT substrate 100, [36], [38], [41], [71]) including, in each of a plurality of subpixels ([38]): a first thin film transistor (LTPS TFT, [4], [41]) including a first semiconductor layer (102, [43]) of a polysilicon ([4]); and a second thin film transistor (TAOS TFT, [6], [41]) including a second semiconductor layer (110, [42]) of an oxide semiconductor ([6]), wherein the first thin film transistor (LTPS TFT, [4], [41]) includes: the first semiconductor layer (102, [43]) including a first conductive region (source/drain 102 in left side of 1021, [47], figure 3) and a second conductive region (source/drain 102 in right side of 1021, [47], figure 3) at a distance from each other; a first gate insulating film (103, [46]) on the first semiconductor layer (102, [43]); a first gate electrode (104, [46]) on the first gate insulating film (103, [46]), the first gate electrode (104, [46]) being configured to control conduction between the first conductive region (source/drain 102 in left side of 1021, [47], figure 3) and the second conductive region (source/drain 102 in right side of 1021, [47], figure 3); an interlayer insulating film (105, [42]) covering the first gate electrode (104, [46]); and a first terminal electrode (106, [50]) and a second terminal electrode (107, [50]) on the interlayer insulating film (105, [42]) at a distance from each other, the first terminal electrode (106, [50]) and the second terminal electrode (107, [50]) being electrically connected respectively to the first conductive region (source/drain 102 in left side of 1021, [47], figure 3) and the second conductive region (source/drain 102 in right side of 1021, [47], figure 3) via a first contact hole (108, [50]) and a second contact hole (108, [50]) formed at least through the interlayer insulating film (105, [42]), the second thin film transistor (TAOS TFT, [6], [41]) includes: the second semiconductor layer (110, [42], [46]) including a third conductive region (source/drain 110 in left side of 111, [47], figure 3) and a fourth conductive region (source/drain 110 in right side of 111, [47], figure 3) at a distance from each other; a first conductive layer (112, [42]) and a second conductive layer (113, [42]) on a base substrate layer side of the third conductive region (source/drain 110 in left side of 111, [47], figure 3) and the fourth conductive region (source/drain 110 in right side of 111, [47], figure 3) respectively, the first conductive layer (112, [42]) and the second conductive layer (113, [42]) being made of a same material ([42]), and provided in a same layer, as the first semiconductor layer (102, [43]); a second gate insulating film (103, [46]) on the second semiconductor layer (110, [42], [46]); a second gate electrode (104, [46]) on the second gate insulating film (103, [46]), the second gate electrode (104, [46]) being configured to control conduction between the third conductive region (source/drain 110 in left side of 111, [47], figure 3) and the fourth conductive region (source/drain 110 in right side of 111, [47], figure 3); the interlayer insulating film (105, [42]) covering the second gate electrode (104, [46]); and a third terminal electrode (106, [50]) and a fourth terminal electrode (107, [50]) on the interlayer insulating film (105, [42]) at a distance from each other, the third terminal electrode (106, [50]) and the fourth terminal electrode (107, [50]) being electrically connected respectively to the first conductive layer (112, [42]) and the second conductive layer (113, [42]) via a third contact hole (108, [50]) and a fourth contact hole (108, [50]) formed at least through the interlayer insulating film (105, [42]), the method comprising: a first semiconductor layer (102, [43]) formation step of forming, on the base substrate layer (100, [41], [71]), the first semiconductor layer (102 for MOS-LTPS, figures) , a first polysilicon layer (102 for 112, figures) that will be the first conductive layer (112, [42]) , and a second polysilicon layer (102 for 113, figures) that will be the second conductive layer (113, [42]) ; a second semiconductor layer (110, [42], [46]) formation step of forming the second semiconductor layer on the first polysilicon layer (102 for 112, figures) and the second polysilicon layer (102 for 113, figures) ; a gate insulating film (103, [46]) formation step of forming the first gate insulating film (103, [46]) and the second gate insulating film (103, [46]) so as to cover the first semiconductor layer (102, [43]) and the second semiconductor layer (110, [42], [46]) respectively; a gate electrode formation (104, [46]) step of forming the first gate electrode (104, [46]) and the second gate electrode (104, [46]) on the first gate insulating film (103, [46]) and the second gate insulating film (103, [46]) respectively; an ion doping step ([47], figure 10) of forming the first conductive region (source/drain 102 in left side of 1021, [47], figure 3) and the second conductive region (source/drain 102 in right side of 1021, [47], figure 3) in the first semiconductor layer (102, [43]) and forming the third conductive region (source/drain 110 in left side of 111, [47], figure 3) and the fourth conductive region (source/drain 110 in right side of 111, [47], figure 3) in the second semiconductor layer (110, [42], [46]) by doping the first semiconductor layer (102, [43]) with impurity ions using the first gate electrode (104, [46]) as a mask and also doping the second semiconductor layer (110, [42], [46]) , the first polysilicon layer (102 for 112, figures) , and the second polysilicon layer (102 for 113, figures) with impurity ions using the second gate electrode (104, [46]) as a mask and of forming the first conductive layer (112, [42]) and the second conductive layer (113, [42]) by modifying the first polysilicon layer (102 for 112, figures) and the second polysilicon layer (102 for 112, figures) into a conductor; an interlayer insulating film (105, [42]) formation step of, after the interlayer insulating film is formed so as to cover the first gate electrode (104, [46]) and the second gate electrode (104, [46]) , forming the first contact hole (108, [50]) , the second contact hole (108, [50]) , the third contact hole (108, [50]) , and the fourth contact hole (108, [50]) at least through the interlayer insulating film (105, [42]) ; and a terminal electrode (106/107, [50]) formation step of forming the first terminal electrode (106, [50]) , the second terminal electrode (107, [50]) , the third terminal electrode (106, [50]) , and the fourth terminal electrode (107, [50]) on the interlayer insulating film (105, [42]) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim (s) 9- 10 and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamaguchi (US 2018/0294286) in view of Son (US 2019/0312061) . Regarding claim 9 , Yamaguchi discloses the display device according to claim 1 as described above. Yamaguchi further discloses, in at least figure s 3, 10-11, 19-21, and related text , a light-emitting element layer (213, [73]) on the thin film transistor layer (layer of TFTs of TFT substrate 100, [36], [38], [41], [71]); and a sealing film (215, [73]) covering the light-emitting element layer (213, [73]). Yamaguchi does not explicitly disclose the light-emitting element layer including a plurality of light-emitting elements corresponding to the plurality of subpixels. Son teaches, in at least figure s 3-5 and related text, the device comprising the light-emitting element layer (layer of 284, [110]) including a plurality of light-emitting elements (284, [110]) corresponding to the plurality of subpixels (PX, [65]) , for the purpose of improv ing electrical characteristics of a thin film transistor thereby improv ing display quality of a display apparatus ([155]) . Yamaguchi and Son are analogous art because they both are directed to display device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yamaguchi with the specified features of Son because they are from the same field of endeavor. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Yamaguchi to have the light-emitting element layer including a plurality of light-emitting elements corresponding to the plurality of subpixels , as taught by Son , for the purpose of improv ing electrical characteristics of a thin film transistor thereby improv ing display quality of a display apparatus ([155]) . Regarding claim 10 , Yamaguchi discloses the display device according to claim 9 as described above. Yamaguchi further discloses, in at least figure s 3, 10-11, 19-21, and related text , the plurality of light-emitting elements (213, [73]) are organic electroluminescence elements ([73]). Regarding claim 12 , Yamaguchi discloses the method according to claim 11 as described above. Yamaguchi further discloses, in at least figure s 3-14, 18-21, and related text , a planarization film (109, [66]) formation step of forming a planarization film so as to cover the first terminal electrode (106, [50]), the second terminal electrode (107, [50]), the third terminal electrode (106, [50]), and the fourth terminal electrode (107, [50]); a light-emitting element layer (213, [73]) formation step on the planarization film (109, [66]) ; and a sealing film (215, [73]) formation step of forming a sealing film so as to cover the light-emitting element layer (213, [73]) . Yamaguchi does not explicitly disclose forming a light-emitting element layer including a plurality of light-emitting elements corresponding to the plurality of subpixels on the planarization film . Son teaches, in at least figures 3-5 and related text, the method comprising forming a light-emitting element layer (layer of 284, [110]) including a plurality of light-emitting elements (284, [110]) corresponding to the plurality of subpixels (PX, [65]) on the planarization film (250, [85]) , for the purpose of improv ing electrical characteristics of a thin film transistor thereby improv ing display quality of a display apparatus ([155]). Yamaguchi and Son are analogous art because they both are directed to method for forming a display device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yamaguchi with the specified features of Son because they are from the same field of endeavor. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Yamaguchi to have the forming a light-emitting element layer including a plurality of light-emitting elements corresponding to the plurality of subpixels on the planarization film , as taught by Son, for the purpose of improv ing electrical characteristics of a thin film transistor thereby improv ing display quality of a display apparatus ([155]). Regarding claim 13 , Yamaguchi discloses the method according to claim 12 as described above. Yamaguchi further discloses, in at least figure s 3-14, 18-21, and related text , the plurality of light-emitting elements (213, [73]) are organic electroluminescence elements ([73]). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. 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