Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation “the chip” in line 12. There is insufficient antecedent basis for this limitation in the claim. It is not clear whether it is referring to different limitation. For purpose of examination, claim 14, line 12 will be treated as stating: “a chip”.
Proper correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 14, 21 and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al. (US 2020/0176346 A1).
Regarding independent claim 1: Wu teaches (e.g., Figs.1A-1I) a fan-out package structure, comprising:
a package substrate ([0011]: 102), having a first side and a second side (bottom side and upper side respectively) opposite to each other in a first direction (vertical direction) and comprising
a first conductive layer ([0011]: 106A) disposed on the second side (upper side);
an RDL structure ([0017]: RDL1), disposed on the second side of the package substrate (upper side of package substrate 102),
wherein the RDL structure comprises at least one dielectric layer ([0014]: 108A) and at least one RDL layer ([0014]: 110A),
the at least one RDL layer (110A) embedded in the at least one dielectric layer (108A) and electrically connected to the first conductive layer (106A),
the at least one dielectric layer and the at least one RDL layer comprise
a first dielectric layer ([0014]: 108A) and a first RDL layer ([0014]: upper portion of 110A), respectively, and
wherein the first RDL layer passes through the first dielectric layer (108A), and be in contact with and electrically connected to the first conductive layer (106A) of the package substrate; and
a chip ([0023]: 134A), disposed on a side of the RDL structure away from the package substrate (102) and electrically connected to the at least one RDL layer (110A) of the RDL structure.
Regarding claim 2: Wu teaches the claim limitation of the fan-out package structure of claim 1, on which this claim depends,
wherein the first RDL layer comprises
a conductive via ([0014]: vertical portion of 110A) and a conductive trace ([0014]: horizontal portion of 110A),
the conductive via is located between the conductive trace ([0014]: horizontal portion of 110A) and the first conductive layer (106A), and electrically connects the conductive trace ([0014]: horizontal portion of 110A) to the first conductive layer (106A).
Regarding claim 3: Wu teaches the claim limitation of the fan-out package structure of claim 2, on which this claim depends,
wherein the conductive via is embedded in the first dielectric layer ([0014]: 108A), and the conductive trace (horizontal portion of 110A) is located on a side of the first dielectric layer away from the package substrate (102).
Regarding claim 4: Wu teaches the claim limitation of the fan-out package structure of claim 1, on which this claim depends,
wherein the first dielectric layer ([0014] and [0017]: 108A) also covers a sidewall of the first conductive layer (106A) of the package substrate and a portion of a surface of a side thereof close to the RDL structure (RDL1).
Regarding claim 5: Wu teaches the claim limitation of the fan-out package structure of claim 1, on which this claim depends,
wherein the package substrate further comprises
a second conductive layer ([0011] and [0013]: 106B) disposed on the first side (bottom side) and a solder mask ([0014]: 108B usable as a solder mask; it protects the surface of a metal layer 106B), and the solder mask covering a sidewall of the second conductive layer (106B) and a portion of a surface of a side (bottom side) thereof away from the RDL structure.
Regarding claim 6: Wu teaches the claim limitation of the fan-out package structure of claim 1, on which this claim depends, further comprises:
an underfill layer ([0024] and [0027]: lower portion chip includes underfill and encapsulant 144 in the lower portion is also an underfill), located between the chip (134A) and the RDL structure (RDL1) in the first direction,
wherein the chip (134A) is electrically connected to the RDL structure (RDL1) via an electrically conductive connector ([0025]: 142), and
the underfill layer ([0024] and [0027]) surrounds the electrically conductive connector (142) in a direction parallel to a main surface of the package substrate (102).
Regarding claim 7: Wu teaches the claim limitation of the fan-out package structure of claim 1, on which this claim depends, further comprises:
an encapsulation layer ([0027]: upper portion of 144), located on the side of the RDL structure (RDL1) away from the package substrate (201), and surrounding and enclosing the chip (134A) at least in a direction parallel to a main surface of the package substrate (201).
Regarding independent claim 14: Wu teaches (e.g., Figs.1A-1I) a manufacturing method of a fan-out package structure, comprising:
providing a package substrate ([0011]: 102),
the package substrate having a first side and a second side (bottom side and upper side respectively) opposite to each other in a first direction (vertical direction) and comprising
a first conductive layer ([0011]: 106A) disposed on the second side;
forming an RDL structure ([0017]: RDL1) on the second side of the package substrate (upper side of package substrate 102),
wherein the RDL structure comprises at least one dielectric layer ([0014]: 108A) and at least one RDL layer ([0014]: upper portion of 110A),
the at least one RDL layer embedded in the at least one dielectric layer (108A) and electrically connected to the first conductive layer (106A),
the at least one dielectric layer and the at least one RDL layer comprise a first dielectric layer (108A) and a first RDL layer (upper portion of 110A), respectively, and
wherein the first RDL layer passes through the first dielectric layer (108A), and be in contact with and electrically connected to the first conductive layer (106A) of the package substrate; and
engaging a chip ([0023]: 134A) to the RDL structure to form an intermediate package member (resulting structure),
wherein the chip is disposed on the side of the RDL structure (RDL1) away from the package substrate (102) and electrically connected to the at least one RDL layer of the RDL structure (RDL1).
Regarding independent claim 21: Wu teaches (e.g., Figs.1A-1I) a fan-out packaging method, comprising:
bonding a first surface (bottom surface) of a package substrate ([0011]-[0012]: 102) to a rigid carrier plate ([0015]: C);
electrically connecting a connection point ([0011] and [0014]: 110A above BL1) on a first surface of an RDL structure (bottom surface of RDL1) to a corresponding connection point ([0014]: 110A below BL1) on a second surface (upper surface) of the package substrate (102);
electrically connecting a pin ([0025]: 142) of a chip to be packaged to a corresponding connection point on a second surface (Fig. 1I; upper surface) of the RDL structure (RDL1) to form a first intermediate package member; and
underfill and molding a gap ([0024] and [0027]: encapsulant 144 underfills and molds) and surrounding of the first intermediate package member.
Regarding claim 23: Wu teaches the claim limitation of the method of claim 21, on which this claim depends,
after the step of electrically connecting a connection point on a first surface of an RDL structure to a corresponding connection point on a second surface of the package substrate ([0017]-[0019]), further comprising:
disposing a passive device ([0020]-[0021]) on the RDL structure (RDL1) such that the passive device forms an electrical connection with the RDL structure ([0020]-[0022]: RDL1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2020/0176346 A1) in view of Nakagawa et al. (US 2017/0033038 A1).
Regarding claim 8: Wu teaches the claim limitation of the fan-out package structure of claim 1, on which this claim depends, further comprises:
Wu does not expressly teach a first passive device, disposed on the side of the RDL structure away from the package substrate and electrically connected to the RDL structure,
wherein the first passive device and the chip are disposed side-by-side in a direction parallel to a main surface of the package substrate.
Nakagawa teaches (e.g., Fig. 6) a fan-out package structure comprising
a first passive device ([0089]: CPS), disposed on a side of a RDL structure ([0073]: WL3/WL2) away from a package substrate ([0075]: 2CR) and electrically connected to the RDL structure (WL3/WL2),
wherein the first passive device (CDC) and a chip ([0072]: CHP2) are disposed side-by-side in a direction parallel to a main surface of the package substrate (2CR).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the package structure of Wu, the first passive device, disposed on the side of the RDL structure away from the package substrate and electrically connected to the RDL structure, wherein the first passive device and the chip are disposed side-by-side in a direction parallel to a main surface of the package substrate, as taught by Nakagawa, for the following benefits of stabilizing the input and output of the signal performed at the high speed (Nakagawa: [0059])
Regarding claim 9: Wu teaches the claim limitation of the fan-out package structure of claim 8, on which this claim depends,
Wu as modified by Nakagawa teaches that the first passive device (Nakagawa: CPS) is enclosed by an encapsulation layer ([0087]-[0088]: UF) located on the RDL structure.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2020/0176346 A1) in view of Lee et al., hereinafter Lee242 (US 2019/0131242 A1).
Regarding claim 10: Wu teaches the claim limitation of the fan-out package structure of claim 1, on which this claim depends, further comprises:
Wu does not expressly teach a second passive device, embedded in the at least one dielectric layer of the RDL structure and electrically connected to the first conductive layer of the package substrate.
Lee242 teaches (e.g., Fig. 9) a fan-out package structure comprising a second passive device ([0096]: inductor is a passive device, to be placed in region 110H), embedded in the at least one dielectric layer ([0066]-[0067] and [0071]: 131) of an RDL structure ([0067]-[0068]: 142) and electrically connected to a first conductive layer (lowermost conductive layer 142) of a package substrate ([0072]: 110).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the packaging of Wu, the second passive device, embedded in the at least one dielectric layer of the RDL structure and electrically connected to the first conductive layer of the package substrate, as taught by Lee242, for the benefits of reducing the residual capacitance of the device by matching the inductive capacitance of induced by the wiring.
Claims 11-13 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2020/0176346 A1) in view of Yeh et al. (US 2022/0310532 A1).
Regarding claim 11: Wu teaches the claim limitation of the fan-out package structure of claim 1, on which this claim depends,
wherein a sidewall of the encapsulation layer (144) and a sidewall of the RDL structure (RDL1) are aligned in the first direction.
Wu does not expressly teach that the package substrate has an extension, and the extension protruding from the sidewall of the encapsulation layer and the sidewall of the RDL structure in a direction parallel to a main surface of the package substrate.
Yeh teaches (e.g., Fig. 17) a package structure comprising
an extension ([0133]-[0135]: 520), and the extension protruding from a sidewall of an encapsulation layer (170, see [0098]) and a sidewall of tan RDL structure (110 see [0097]) in a direction parallel to a main surface of the package substrate ([0121]: 310).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the device of Wu, the package extension, wherein the extension protrudes from the sidewall of the encapsulation layer and the sidewall of the RDL structure in a direction parallel to a main surface of the package substrate, as taught by Yeh, for the benefits of improving the thermal dissipation of the packaging and protecting the device from thermal damage.
Regarding claim 12: Wu and Yeh teach the claim limitation of the fan-out package structure of claim 11, on which this claim depends, further comprising:
Wu as modified by Yeh teaches a heat sink member (Yeh: [0134]-[0136] and [0138]: 540), disposed on the extension of the package substrate (Yeh: 310) and affixed to a surface of a side of the chip away from the RDL structure (Wu: RDL1).
Regarding claim 13: Wu and Yeh teach the claim limitation of the fan-out package structure of claim 12, on which this claim depends, further comprises:
Wu as modified by Yeh teaches a heat sink layer (Yeh: [135]: 550), disposed on the surface of a chip (240, see [0097]), and the heat sink member (Yeh: 540) is affixed to the surface of the chip by the heat sink layer (Yeh: 550).
Regarding claim 24: Wu teaches the claim limitation of the method of claim 21, on which this claim depends,
Wu does not expressly teach that after the step of underfill and molding a gap and surrounding of the intermediate package member, further comprising:
thinning a molding material to expose a backside of the chip to form a second intermediate package member; disposing a heat sink metal layer on a backside of the second intermediate package member.
Yeh teaches (e.g., Fig. 17) a method comprising forming a package substrate ([0121]: 310).
Yeh further teaches that after the step of underfill and molding (170, see [0098]) a gap and surrounding of an intermediate package member ([0106], [0121]: 310), further comprising:
thinning a molding material ([0085]-[0086]: the planarizing step is performed on the over-molded insulating encapsulation) to expose a backside of the chip ([0086]-[0087]; Fig, 14A corresponds to packaging after thinning of the molding material 170) to form a second intermediate package member (resulting structure);
disposing a heat sink metal layer ([0133]-[0134]: 540) on a backside of the second intermediate package member (resulting structure).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, the method of Wu, the method of Yeh, wherein after the step of underfill and molding a gap and surrounding of the intermediate package member, further comprises thinning a molding material to expose a backside of the chip to form a second intermediate package member; disposing a heat sink metal layer on a backside of the second intermediate package member, as taught by Yeh, for the benefit of increasing device cooling during operation, thus protecting the device from thermal damage.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2020/0176346 A1) in view of Lee et al., hereinafter Lee 933 (US 2019/0164933 A1).
Regarding claim 22: Wu teaches the claim limitation of the method of claim 21, on which this claim depends,
Wu does not expressly teach that before the step of electrically connecting a connection point on a first surface of an RDL structure to a corresponding connection point on a second surface of the package substrate, further comprising:
disposing a passive device on the package substrate such that the passive device forms an electrical connection with the package substrate.
Lee933 teaches (e.g., Figs. 13A-14E) a method comprising
before a step of electrically connecting a connection point (112c) on a first surface of an RDL structure ([0120]: bottom surface of RDL 140) to a corresponding connection point on a second surface (upper surface) of a package substrate ([108] and [0113]: 111a), further comprising:
disposing a passive device ([0098]: ”a separate passive component such as an inductor, a capacitor, or the like, is disposed in the recess portion 110H) on the package substrate such that the passive device forms an electrical connection (metal material lining the substrate; see [0073]-[0074]: devices in the substrate have connection with the substrate) with the package substrate (111a).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Wu, the comprising before the step of electrically connecting a connection point on a first surface of an RDL structure to a corresponding connection point on a second surface of the package substrate, further comprises disposing a passive device on the package substrate such that the passive device forms an electrical connection with the package substrate, as taught by Lee933, for the benefits of reducing the residual capacitance of the integrated circuit.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2020/0176346 A1) in view of Yu et al. (US 2019/0051604 A1).
Regarding claim 25: Wu teaches the claim limitation of the method of claim 21, on which this claim depends.
after the step of underfill and molding ([0024] and [0027]: 144) a gap and surrounding of the first intermediate package member, further comprising:
debonding the rigid carrier plate ([0028]: carrier C is de-bonded) to the package substrate and removing residual bonding adhesive ([0028]: carrier C is de-bonded this is interpreted as including any material used for the bonding process; thus this meets the claim limitation requirement); and
Wu does not expressly teach that
sawing the package substrate and the RDL structure to form a package monomer with a predetermined number of chips.
Yu teaches (e.g., Figs. 4A-1K) a method comprising a package substrate ([0059]: 132) and a RDL structure ([0059]: 110),
sawing the package substrate ([0063]: sawing the package substrate) and the RDL structure to form a package monomer with a predetermined number of chips ([0063]: 120/140).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Wu, the process of sawing the package substrate and the RDL structure to form a package monomer with a predetermined number of chips, as taught by Yu, for the benefits of increasing the packaging density by allowing stacking of the devices without increasing the span of the integrated circuit, such that the device foot print is reduced.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2020/0176346 A1) in view of Yu et al. (US 2019/0051604 A1) as applied above and further in view of Yeh et al. (US 2022/0310532 A1).
Regarding claim 27: Wu teaches the claim limitation of the method of claim 25, on which this claim depends.
Wu does not expressly teach that then method further comprises
connecting the package monomer to a heat sink cover,
wherein a backside of the chip of the package monomer contacts the heat sink cover through a thermally conductive material.
Yeh teaches (e.g., Figs 13A-17) a method comprising a chip (240, see [0098])
connecting the package monomer to a heat sink cover ([0134]-[0136] and [0138]: 540);
wherein a backside of the chip (240, see [0098]) of a package monomer ([0125] and [0129]) contacts the heat sink cover ([0134]-[0136] and [0138]: 540) through a thermally conductive material ([0135]-[0136]: 550).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include n the method of Wu, the method of connecting the package monomer to a heat sink cover, wherein a backside of the chip of the package monomer contacts the heat sink cover through a thermally conductive material, as taught by Yeh, for the benefits of increasing heat dissipation away from the and thus increasing reliability by reducing potential thermal damage of the device in operation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812
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