DETAILED ACTION
Status of the Claims
1. Claims 1-7 are being examined in this application
Claims 8-22 are withdrawn.
Election/Restrictions
2. Applicant’s election without traverse of claims 1-7 in the reply filed on 5/01/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 2020/0292521) in view of Su et al. (CN1860370, examiner is using English machine translation).
Claims 1 and 6. Xie et al. teach a nanopore device (nanopore sensor 102; [0183]), comprising:
an application specific integrated circuit (ASIC) layer (integrated circuit layer 150 which is specific to nanopore sensing [0198], thus integrated circuit layer reads on ASIC; [0198] and Fig 3b), wherein the ASIC layer comprises active circuitry on a front side semiconductor wafer (integrated circuit is comprised of electronic circuit on a front of CMOS wafer; [0186]):
a post array layer under the ASIC layer, wherein the post array layer comprises an array of posts on a front side of a support substrate (array of channels 122a on a front side of base layer 112 and disposed under the integrated circuit layer 150; [0207] and Fig 4b) and
a nanopore layer over the ASIC layer, wherein the nanopore layer comprises a plurality of middle chambers over the active circuitry, a membrane on the plurality of middle chambers, and a plurality of nanopores inserted in the membrane over the plurality of middle chambers (nanopore layer 110 over the integrated circuit layer 150, the nanopore layer comprises plurality of wells 142, a membrane 118 on the plurality of wells 142 and plurality of nanopores 116 in the membrane ([0188][0202] and Fig 3b and 4a).
Xie et al. do not teach integrate circuit layer comprises a thinned-down semiconductor wafer.
However, Su et al. teach method of forming nanopore device comprised of electronic components as part of integrated circuit deposited on substrate film with thickness range of several nanometers to 100 microns [0081].
Since Su et al. and Xie et al. are to same field of endeavor i.e. nanopore device comprising integrated circuitry, therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention in view of Su et al. teaching to construct the integrated circuit layer of Xie et al. of thin substrate layer having thickness in the range several nanometers to 100 microns because applying a known technique to a known device (method or product) ready for improvement to yield predictable results is likely to be obvious (see MPEP § 2143, D.).
Claim 2. Xie et al. teach nanopore device further comprising:
a cis chamber over the nanopore layer, wherein at least one of the plurality of nanopores fluidically connects the cis chamber to at least one of the plurality of middle chambers (cis chamber 106 over the nanopore layer and nanopore 116 fluidically connect the cis chamber to middle chamber 142; see Fig 3a and [0160][0202]); and
a trans chamber under the ASIC layer, wherein the trans chamber comprises the array of posts (outlet chamber 108 is under the integrated circuit layer 150; see Fig 3b, wherein the chamber comprises the array of channels 122 of base layer 112; see Figs 4b, 9).
Claim 3. Xie et al. teach a plurality of fluidic channels extending through the ASIC layer, wherein at least one of the plurality of fluidic channels fluidically connects at least one of the plurality of middle chambers to the trans chamber (channels 114 forms fluidic passage which extends into the integrated circuit layer and connects the chamber 142 to the outlet chamber 108; see Fig 3b and [0176]).
Claim 4. Xie et al. teach at least one of the plurality of fluidic channels comprises a horizontal channel and a vertical channel (channel 114 (vertical channel) is connected to horizontal section 146 to fluidically connect the chamber 142 to the outlet chamber 108; see Fig 3b).
Claim 5. Xie et al. teach a fluid inlet and a fluid outlet reaching the trans chamber through the nanopore layer and the ASIC layer (Fig 3b shows fluid flows through the cis chamber 106 through the nanopore layer into the integrated circuit layer and into the trans chamber via 114 passage; see Fig 3b and [0175]).
Claim 7. Xie et al. teach the support substrate comprises silicon, semiconductor, sapphire, dielectric, polymer or glass (the base layer 112 is made up of silicon wafer; [0186]).
Conclusion
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/GURPREET KAUR/
Primary Examiner
Art Unit 1759
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