Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/05/2026 has been entered.
Based on the foreign documents submitted in 08/05/2026 IDS, previous allowance of claims 3-4 has been withdrawn. A new ground of rejection has been applied as described below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Norihiko et al. (JP 2009231550 A) in view of Akira et al. (JP H07297488 A; hereinafter “Akira”) (all the page and paragraph numbers are referring to the attached English translations of Norihiko and Akira).
In re claim 3, Norihiko discloses in figs. 1-6, a method for manufacturing a substrate for a semiconductor device, the method comprising steps of:
(1) preparing a laminated substrate including:
a high-resistant silicon single crystal substrate having a resistivity of 100 Ω-cm or more (e.g., 6 KΩ-cm) (page 7; 7th paragraph; “Here, an n-type Si substrate having a (111) plane as a main surface and manufactured by the FZ method and having a resistivity ρ of 6 [kΩ.cm] or more is used as the growth substrate.”);
a first buffer layer composed of an AlN layer and formed on a top surface of the high-resistant silicon single crystal substrate (page 8, 1st paragraph); and
a nitride semiconductor layer (e.g., AlGaN layer) provided on the first buffer layer (page 8, 1st paragraph).
Norihiko discloses when the substrate temperature is raised to 1200 [° C.] and an AlN 1layer is formed on the Si substrate, the resistance value of the Si substrate decreases and an object of the present invention is to manufacture a semiconductor device that suppresses a decrease in the resistance value of an Si substrate when AlN and GaN are grown on the Si substrate (see pages 2-3).
However, Norihiko does not expressly disclose the second step, i.e.,
(2) irradiating the laminated substrate with electron beam from a rear surface side of the high-resistant silicon single crystal substrate to erase a low-resistivity portion formed on a top surface of the high-resistant silicon single crystal substrate,
the low-resistivity portion having a resistivity relatively lower than the resistivity of an entirety of the high-resistant silicon single crystal substrate.
In the same field of endeavor, Akira discloses (see paragraphs 1-16 of the specification, Figures 1-2) a method for producing a semiconductor thin film crystal and a semiconductor laser. In the semiconductor thin film crystal growth, a specific region having any shape is irradiated with charged particles such as electrons or ions of a specific element, so that the irradiated region becomes a high-resistance region (i.e., a process of eliminating a low-resistivity portion; irradiation with an electron ray eliminates a low-resistivity portion). Whereas the effect of irradiating the semiconductor region by electron beam so that the irradiated region becomes a high-resistive zone is the same as that of this claim.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to suppress a decrease in the resistance value of an Si substrate when AlN and GaN are grown on the Si substrate of Norihiko and form a high resistance region by irradiating the laminated substrate with electron beam from a rear surface side of the high-resistant silicon single crystal substrate as disclosed by Akira to control and to realize a high-performance semiconductor laser by making a specific region having an arbitrary shape a high resistance region during the growth of a semiconductor thin film (see pages 1-3 of Akira).
In re claim 4, Norihiko, as modified by Akira, discloses the method for manufacturing a substrate for a semiconductor device according to claim 3 outlined above.
Norihiko further discloses in figs. 1-6, wherein the nitride semiconductor layer provided on the first buffer layer is:
a second buffer layer (e.g., AlGaN) composed of a nitride semiconductor layer provided on the first buffer layer AlN; and
a device active layer (e.g., GaN) composed of a nitride semiconductor layer provided on the second buffer layer AlGaN (page 8, paragraphs 1-4).
Conclusion
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893
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