Prosecution Insights
Last updated: August 16, 2026
Application No. 18/580,309

DISPLAY APPARATUS AND METHOD FOR MANUFACTURING DISPLAY APPARATUS

Non-Final OA §DP
Filed
Jan 18, 2024
Priority
Jul 21, 2021 — JP 2021-120393 +1 more
Examiner
WALL, VINCENT
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Semiconductor Energy Laboratory Co., Ltd.
OA Round
1 (Non-Final)
62%
Grant Probability
Moderate
1-2
OA Rounds
2m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allowance Rate
507 granted / 815 resolved
-5.8% vs TC avg
Strong +24% interview lift
Without
With
+24.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
60 currently pending
Career history
871
Total Applications
across all art units

Statute-Specific Performance

§101
2.5%
-37.5% vs TC avg
§103
52.4%
+12.4% vs TC avg
§102
16.2%
-23.8% vs TC avg
§112
25.1%
-14.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 815 resolved cases

Office Action

§DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group I, Species A1 and B2, represented by figures 2A-3B and 19, claims 1-9 in the reply filed on July 7, 2026 is acknowledged. Applicant states they also elect species 4 (figure 3D). This appears to be a typographical error as there was no species 4 in the restriction/election requirement and there is no figure 3D in drawings filed January 18, 2024. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on February 7, 2025; October 7, 2024; and February 12, 2024 were considered by the examiner. Drawing Objections The numerous drawings have not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the drawings. Specification Objections The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. At least one of claims 1-9 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over at least one of claims 1-10 of copending Application No. 18/569,769 (US PGPub 2024/0292669 A1) (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the current application’s claim(s) read upon the copending application’s claim(s), and vice-versa. This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. Allowable Subject Matter Claims 1-9 are allowable if the double patenting is overcome. The following is an examiner’s statement of reasons for allowance: see below. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Regarding claim 1, The prior art does not teach the limitations of claim 1 because the prior art does not teach: a third insulating layer in contact with a part of a top surface of the first EL layer, and a common electrode over the first EL layer and the third insulating layer, a fourth insulating layer in contact with a part of a top surface of the second EL layer, and the common electrode over the second EL layer and the fourth insulating layer, wherein the first insulating layer is in contact with a top surface and a side surface of the third insulating layer, wherein at least a part of the second insulating layer is provided to be sandwiched between an end portion of the side surface of the first EL layer and an end portion of the side surface of the second EL layer, wherein the second insulating layer has a tapered side surface and a convex shaped top surface in a cross-sectional view, wherein a taper angle of the tapered side surface of the second insulating layer is less than 90° and wherein the common electrode overlaps with the second insulating layer. Regarding claim 2, Claim 2 is allowable for the same reasons as claim 1 above. The closest prior art is… US 2015/0069360 A1, this does not teach the third/fourth insulating layer with the first first/second insulating layer; US 2016/0315133 A1; US 2019/0043934 A1, this does not teach the third/fourth insulating layer contacts (e.g. directly contacts) the top surface of the EL layer; US 10,439,160 B2, this does not teach the limitations above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT WALL whose telephone number is (571)272-9567. The examiner can normally be reached Monday to Thursday at 7:30am to 2:30pm PST. Interviews can be scheduled on Tuesday thru Thursday at 10am PST or 2pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VINCENT WALL/Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Jan 18, 2024
Application Filed
Jul 23, 2026
Non-Final Rejection mailed — §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
62%
Grant Probability
86%
With Interview (+24.3%)
2y 9m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 815 resolved cases by this examiner. Grant probability derived from career allowance rate.

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