DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This OA is in response to the amendment filled on 6/29/2026 that has been entered, wherein claims 1, 3-4 and 6-11 are pending and claims 2 and 5 are canceled.
Specification
The objection to the specification is withdrawn in light of Applicant’s amendment of 6/29/2026.
Claim Rejections - 35 USC § 112
The 35 USC rejection of claims 1-11 are withdrawn in light of Applicant’s amendment of 6/29/2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3-4, 6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Nagasawa et al. (JP 2007/019394 A) of record in view of Lee et al. (US 2015/0366059 A1).
Regarding claim 1, Nagasawa teaches a chip carrier structure(Fig. 1) being defined with a chip carrier region and a wire bonding region located around the chip carrier region, the chip carrier structure comprising:
an insulating layer(3, ¶0009);
a circuit layer(4, ¶0009) formed on the insulating layer(3, ¶0009);
a solder mask layer(6, ¶0009) formed on the insulating layer(3, ¶0009) and the circuit layer(4, ¶0009), wherein a plurality of openings(6’, Fig. 11, ¶0009, ¶0014) are formed in the wire bonding region and expose portions of the circuit layer(4, ¶0009) and portions of the insulating layer(3, ¶0009); and
a protective layer(Au plating, Fig. 11, ¶0014) formed and stacked on the portions of the circuit layer(4, ¶0009) exposed from the openings(6’, Fig. 11, ¶0009, ¶0014) of the solder mask layer(6, ¶0009);
wherein at least one spacer portion(space between adjacent bonding fingers 4’, Fig. 2, ¶0009) is formed on the portions of the circuit layer(4, ¶0009) exposed from each of the openings(6’, Fig. 11, ¶0009, ¶0014) and divides the portions of the circuit layer(4, ¶0009) exposed from the openings(6’, Fig. 11, ¶0009, ¶0014) of the solder mask layer(6, ¶0009) into at least two blocks(4,’ ¶0014),
wherein the protective layer(Au plating, Fig. 11, ¶0014) is disposed with at least one soldering finger region(region of wire 8, ¶0009) thereabove.
Nagasawa is not relied on to teach an area of the protective layer(Au plating, Fig. 11, ¶0014) exposed from each of the openings(6’, Fig. 11, ¶0009, ¶0014) is larger than an area of the soldering finger region(region of wire 8, ¶0009) and at the same time smaller than or equal to an area of the circuit layer(4, ¶0009) exposed from each of the openings(6’, Fig. 11, ¶0009, ¶0014).
Lee teaches a chip carrier structure(Fig. 1) wherein an area of the protective layer(140, ¶0032) exposed from each of the openings(121, ¶0030) is larger than an area of the soldering finger region(region of 220, ¶0028) and at the same time smaller than or equal to an area of the circuit layer(130, 111, ¶0028) exposed from each of the openings(121, ¶0030). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Nagasawa, so that an area of the protective layer exposed from each of the openings is larger than an area of the soldering finger region and at the same time smaller than or equal to an area of the circuit layer exposed from each of the openings, as taught by Lee, in order to prevent oxidation or pollution on a surface of the circuit layer and to allow a wire, the solder, or the like, to be tightly coupled to the circuit layer(¶0032) and to improving a degree of integration of the circuit layer(¶0033).
Regarding claim 3, Nagasawa teaches the chip carrier structure of claim 1, wherein the protective layer(Au plating, Fig. 11, ¶0014) is composed of gold(¶0014).
Regarding claim 4, Nagasawa teaches the chip carrier structure of claim 1, wherein the circuit layer(4, ¶0009) is composed of copper(¶0011) or copper-containing alloy.
Regarding claim 6, Nagasawa teaches the chip carrier structure of claim 1, wherein a thickness of the protective layer(Au plating, Fig. 11, ¶0014) is less(Fig. 11) than a thickness of the circuit layer(4, ¶0009).
Regarding claim 9, Nagasawa teaches the chip carrier structure of claim 1, wherein the spacer portion(space between adjacent bonding fingers 4’, Fig. 2, ¶0009) has a width greater than or equal(Fig. 3) to a minimum line spacing [of the bonding fingers 4’].
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Nagasawa et al. (US 2007/019394 A) of record and Lee et al. (US 2015/0366059 A1) as applied to claim 1 above, further in view of Chinda et al. (US 2002/0074667 A1) of record.
Regarding claim 7, Nagasawa, in view of Lee, teaches the chip carrier structure of claim 1, but is not relied on to teach the protective layer(Au plating, Fig. 11, ¶0014) has a thickness between 0.3 μm and 1.2 μm.
Chinda teaches a chip carrier structure(Fig. 8) wherein the protective layer(gold plating layer plating, ¶0065) has a thickness between 0.3 μm and 1.2 μm(¶0065). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Nagasawa, so that the protective layer has a thickness between 0.3 μm and 1.2 μm, as taught by Chinda, so that connection reliability of the conductive member and an external device can be improved(¶0032).
Claims 8 and 11 is rejected under 35 U.S.C. 103 as being unpatentable over Nagasawa et al. (US 2007/019394 A) of record and Lee et al. (US 2015/0366059 A1) as applied to claim 1 above, further in view of Narvaez et al. (US 6396135 B1) of record.
Regarding claim 8, Nagasawa, in view of Lee, teaches the chip carrier structure of claim 1, does not explicitly state the area of the protective layer(Au plating, Fig. 11, ¶0014) exposed from each of the openings(6’, Fig. 11, ¶0009, ¶0014) is less than 70000 μm2.
Narvaez teaches a chip carrier structure(Fig. 3) and that it is generally desirable to minimize the amount of protective layer underneath the solder mask layer(col. 4, lines 6-14) while also maximizing the amount of portions of the insulating layer exposed from the plurality of openings 117 in the solder mask layer 115(col. 3, lines 30-55). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Nagasawa to make the area of the protective layer exposed from each of the openings is less than 70000 μm2, since it has been held that when the prior art discloses the general conditions of the claimed invention, discovering the optimum or workable ranges involves only ordinary skill in the art. See MPEP 2144.05. Accordingly, a person of ordinary skill in the art would use routine optimization to make the area of the protective layer exposed from each of the openings is less than 70000 μm2, in order to improve the adhesion of molding material to the chip carrier structure and thus the environmental resistance of the resulting package(col. 3, lines 30-55).
Regarding claim 11, Nagasawa, in view of Lee, teaches the chip carrier structure of claim 1, does not explicitly state a ratio of the area of the protective layer(Au plating, Fig. 11, ¶0014) exposed from each of the openings(6’, Fig. 11, ¶0009, ¶0014) to an area of the insulating layer(3, ¶0009) exposed from each of the openings(6’, Fig. 11, ¶0009, ¶0014) is less than or equal to 20%.
Narvaez teaches a chip carrier structure(Fig. 3) and that it is generally desirable to minimize the amount of protective layer underneath the solder mask layer(col. 4, lines 6-14) while also maximizing the amount of portions of the insulating layer exposed from the plurality of openings 117 in the solder mask layer 115(col. 3, lines 30-55). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Nagasawa to make a ratio of the area of the protective layer exposed from each of the openings to an area of the insulating layer exposed from each of the openings is less than or equal to 20%, since it has been held that when the prior art discloses the general conditions of the claimed invention, discovering the optimum or workable ranges involves only ordinary skill in the art. See MPEP 2144.05. Accordingly, a person of ordinary skill in the art would use routine optimization to make a ratio of the area of the protective layer exposed from each of the openings to an area of the insulating layer exposed from each of the openings is less than or equal to 20%, in order to improve the adhesion of molding material to the chip carrier structure and thus the environmental resistance of the resulting package(col. 3, lines 30-55).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Nagasawa et al. (US 2007/019394 A) of record and Lee et al. (US 2015/0366059 A1) as applied to claim 1 above, further) in view of Shimanuki (US 2006/0091523 A1) of record.
Regarding claim 10, Nagasawa, in view of Lee, teaches the chip carrier structure of claim 1, but is not relied on to teach the spacer portion(space between adjacent bonding fingers 4’, Fig. 2, ¶0009) has a width greater than or equal to 100 μm.
Shimanuki teaches a chip carrier structure(Fig. 30) wherein the spacer portion(space between adjacent connecting terminals, ¶00124) has a width(L1) greater than or equal to 100 μm(¶0124). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Nagasawa, so that the spacer portion(space between adjacent bonding fingers 4’, Fig. 2, ¶0009) has a width greater than or equal to 100 μm, as taught by Shimanuki, to reduce size/area of the chip carrier structure(¶0124).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yu et al. (US 2024/0120300 A1) Discloses a chip carrier structure.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA DYKES whose telephone number is (571)270-3161. The examiner can normally be reached M-F 9:30 am-5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAURA M DYKES/Examiner, Art Unit 2892
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