DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following items from the applicant: Information Disclosure Statement (IDS) filed on 19 February 2024. The references cited on the PTOL 1449 form have been considered.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites “wherein the first channel portion comprises … a height along a vertical direction” however the height was already introduced in parent claim 9 “a height of the first channel portion.” Therefore, it is unclear if applicant is referring to the same height of the parent claim or a different height with an unknown relationship. If the applicant intended to further limit the height of the first channel portion as established in claim 9 to be in the vertical direction, then claim 11 should be amended to reference the antecedent height.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. (U.S. Patent 9,984936).
Referring to Claim 9, Xie teaches in Fig. 14, 16 and 23 for example, a semiconductor device, comprising: a first transistor comprising: a first source/drain feature (142) and a second source/drain feature (142), a first nanostructure (106) disposed over and spaced apart from a first base portion (102 and/or 128), and a first gate structure (146) wrapping around the first nanostructure (106), wherein the first nanostructure (106) extends lengthwise between the first source/drain feature (142) and the second source/drain feature (142) along a first direction, wherein the first nanostructure (106) includes a first channel portion directly under the first gate structure (146) and a first connection portion between the first channel portion and the first source/drain feature (142) along the first direction, and wherein a height of the first connection portion is greater than a height (106x) of the first channel portion (Col. 10, Line 53 to Col. 11, Line 51).
Referring to Claim 13, Xie further teaches a second transistor comprising: a third source/drain feature (142) and a fourth source/drain feature (142), a second nanostructure (106) disposed over and spaced apart from a second base portion (102 and/or 128), and a second gate structure (146) wrapping around the second nanostructure (106).
Claims 9, 13 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (U.S. Patent Application Publication 2018/0061944).
Referring to Claim 9, Cheng teaches a semiconductor device, comprising: a first transistor (160) comprising: a first source/drain feature (106 left) and a second source/drain feature (106 right), a first nanostructure (one of 162) disposed over and spaced apart from a first base portion (portion of substrate 102 between shallow trench isolation regions 104), and a first gate structure (par. 28 and 25) wrapping around the first nanostructure (one of 162), wherein the first nanostructure (one of 162) extends lengthwise between the first source/drain feature (106 left) and the second source/drain feature (106 right) along a first direction (left to right in Fig. 5), wherein the first nanostructure (one of 162) includes a first channel portion (central portion of 162) directly under the first gate structure and a first connection portion (portion of 162 masked by sidewall spacers 168) between the first channel portion (central portion of 162) and the first source/drain feature (106 left) along the first direction, and wherein a height of the first connection portion (portion of 162 masked by sidewall spacers 168) is greater than a height of the first channel portion (central portion of 162) (channels are thinned; par. 27 and 30).
Referring to Claim 13, Cheng further teaches a second transistor (130) comprising: a third source/drain feature (106 left) and a fourth source/drain feature (106 right), a second nanostructure (one of 132) disposed over and spaced apart from a second base portion (portion of substrate 102 between shallow trench isolation regions 104), and a second gate structure (par. 28 and 29) wrapping around the second nanostructure (one of 132).
Referring to Claim 14, Cheng further teaches wherein the second nanostructure (one of 132) extends lengthwise between the third source/drain feature (106 left) and the fourth source/drain feature (106 right) along the first direction (left to right in Fig. 5),
wherein the second nanostructure (one of 132) includes a second channel portion (central portion of 132) directly under the second gate structure and a second connection portion (portion of 132 masked by sidewall spacers 118) between the second channel portion (central portion of 132) and the third source/drain feature (106 left) along the first direction (left to right in Fig. 5), and wherein a height of the second connection portion (portion of 132 masked by sidewall spacers 118) is similar to a height of the second channel portion (central portion of 132) (channels were not thinned as they were masked by 440 during the thinning of the first transistor 160).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 11, 12 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (U.S. Patent 9,984936) or Cheng et al. (U.S. Patent Application Publication 2018/0061944), in view of Lilak et al. (U.S. Patent Application Publication 2020/0098756).
As insofar as Claim 11 is definite, Xie and Cheng respectively teach the limitations of claim 9 wherein the first channel portion comprises a width along a second direction perpendicular to the first direction and a height along a vertical direction, but do not explicitly state wherein the width of the first channel portion is smaller than the height of the first channel portion, per se.
Lilak teaches in Fig. 1A-1B and 5, a transistor in region (106) having nanostructures (132) wherein the first channel portion (130) comprises a width along a second direction perpendicular to the first direction and a height along a vertical direction, wherein the width of the first channel portion (130) is smaller than the height of the first channel portion (130) (par. 40).
It would have been obvious to one having ordinary skill in the art before the invention was effectively filed to utilize the shape of the channel portion taught by Lilak for that of Xie or Cheng in order to provide the desired beneficial strain in the channel to improve carrier mobility and transistor performance (par. 21-26).
As insofar as Claim 12 is definite, as modified above Xie or Cheng, in view of Lilak teach the limitations of claim 11 but does not explicitly state wherein the width of the first channel portion is between about 3 nm and about 7 nm, wherein the height of the first channel portion is between about 5 nm and about 15 nm.
Lilak does teach the channel portion to have a height that is at least 1.5 times the width, including at least 2 times, at least 3 times, at least 5 times, at least 10 times, or other amount (par. 40) and the techniques may be used to benefit devices of varying scales, such as IC devices having critical dimensions in the micrometer (micron) range and/or in the nanometer (nm) range (e.g., formed at the 22, 14, 10, 7, 5, or 3 nm process nodes, or beyond) (par. 33). Lilak also teaches that in some embodiments, each fin 160 may include a vertical fin height (dimension in the Z-axis direction) in the range of 20-500 nm (or in a subrange of 20-50, 20-100, 20-200, 20-300, 20-400, 50-100, 50-200, 50-300, 50-400, 50-500, 100-250, 100-400, 100-500, 200-400, or 200-500 nm) and/or a maximum vertical fin height of at most 500, 450, 400, 350, 300, 250, 200, 150, 100, or 50 nm, for example. In some embodiments, each fin may include a horizontal fin width (dimension in the X-axis direction) in the range of 2-50 nm (or in a subrange of 2-5, 2-10, 5-10, 5-20, 5-30, 5-50, 10-20, 10-30, 10-50, 20-30, 20-50, or 30-50 nm) and/or a maximum horizontal fin width of at most 50, 30, 20, 10, or 5 nm, for example. In some embodiments, the ratio of fin height to fin width may be greater than 1, such as greater than 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9, 10, 15, 20, or greater than any other suitable threshold ratio (par. 71).
It would have been obvious to one of ordinary skill in the art before the invention was effectively filed to select the dimensions of the claimed range to achieve the desired beneficial strain in the channel, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Referring to Claim 17, Xie and Cheng each respectively teach the limitations of claim 13.
While Xie does not explicitly state wherein the first source/drain feature and the second source/drain feature comprise a first semiconductor material and a p-type dopant, wherein the third source/drain feature and the fourth source/drain feature comprise a second semiconductor material and an n-type dopant, Xie does teach that the source/drain features (142) may be doped in situ with the appropriate dopant type (N or P) depending upon the type of device (N or P) under construction.
Cheng inherently teaches wherein the first and second source/drain features (106) comprise a first semiconductor material and dopant, and wherein the third and fourth source/drain features (106) comprise a second semiconductor material and a dopant, but does not explicitly state wherein the first and second source/drain features comprise a p-type dopant, or wherein the third and fourth source/drain features comprise an n-type dopant, per se.
In the same field of endeavor, Lilak teaches the well-known CMOS structure of having PMOS and NMOS nanostructure transistors with each type having different structural features to benefit their respective carrier’s mobility (par. 40-42).
It would have been obvious to one having ordinary skill in the art before the invention was effectively filed to provide respective p-type and n-type dopants for the source/drain features as taught by Lilak for the respective transistors of Xie or Cheng to provide the benefits of having both NMOS and PMOS transistor types to minimize power consumption.
Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (U.S. Patent 9,984936) or Cheng et al. (U.S. Patent Application Publication 2018/0061944), in view of Glass et al. (U.S. Patent Application Publication 2020/0258982).
Referring to Claim 15, Xie and Cheng each respectively teach the limitations of claim 13.
Xie further teaches a first source/drain contact (150) disposed over the first source/drain feature (142); and a second source/drain contact (150) disposed over the third source/drain feature (142), wherein the first source/drain contact (150) comprises a first contact width along a second direction perpendicular to the first direction, wherein the second source/drain contact (150) comprises a second contact width along the second direction.
Cheng further teaches a first source/drain contact (550) disposed over the first source/drain feature (106); and a second source/drain contact (550) disposed over the third source/drain feature (106), wherein the first source/drain contact (550) comprises a first contact width along a second direction perpendicular to the first direction, wherein the second source/drain contact (550) comprises a second contact width along the second direction.
Xie and Cheng each do not explicitly state wherein the second contact width is greater than the first contact width.
Glass teaches forming different transistors each having nanostructures (275) with respective channel portions and each transistor having respectively source/drain features (261 of one transistor and 262 of another transistor). The source/drain features of the respective transistors have source/drain contacts of differing widths (Fig. 2P-2T).
It would have been obvious to one having ordinary skill in the art before the invention was effectively filed to provide the first and second contacts of Xie or Cheng to have the second contact having a width greater than the first contact width as taught by Glass in order to achieve the desired current capacity through the respective transistors.
Referring to Claim 16, as modified above, Xie or Cheng in view of Glass teach the limitations of claim 15.
Glass does not explicitly state wherein a ratio of the second contact width to the first contact width is between about 2 and about 10.
However, it would have been obvious to one of ordinary skill in the art before the invention was effectively filed to adjust the widths to have a ratio in the claimed range in order to achieve the desired current capacity through the respective source/drain features of the transistors, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Absent a showing of criticality with respect to ratio of widths (a result effective variable), it would have been obvious to a person of ordinary skill in the art at the time the invention was effectively filed to adjust the widths through routine experimentation in order to achieve varying current capacity through the respective transistors. It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (U.S. Patent Application Publication 2018/0061944), in view of Lilak et al. (U.S. Patent Application Publication 2020/0098756) or Hsu et al. (U.S. Patent Application Publication 2020/0006478).
Referring to Claim 18, Cheng teaches a method, comprising: depositing, on a substrate (102), a stack comprising a plurality of silicon layers interleaved by a plurality of silicon germanium layers; patterning the stack and the substrate (102) into a first fin-shaped structure (right side transistor 160) having a first width along a first direction (into/out of page) and a second fin-shaped structure (left side transistor 130) having a second width along the first direction (into/out of page); forming a first dummy gate stack (114) over a first channel region of the first fin-shaped structure (right side transistor 160) and a second dummy gate stack (114) over a second channel region of the second fin-shaped structure (left side transistor 130) (block 602; par. 20-23 and 31; Fig. 1 and 6); removing the first dummy gate stack (114) and the second dummy gate stack (114) (block 604; par. 24 and 31; Fig. 2 and 6); selectively removing the silicon germanium layers in the first channel region and the second channel region to form first nanostructures (162) in the first channel region and second nanostructures (132) in the second channel region (block 606; par. 25 and 31; Fig. 3 and 6); selectively trimming the first nanostructures (162) in the first channel region to form trimmed first nanostructures (162), while the second channel region is covered by a mask (440) (block 608-612; par. 26-27 and 31; Fig. 4 and 6); forming a first gate structure to wrap around each of the trimmed first nanostructures (162); and forming a second gate structure to wrap around each of the second nanostructures (132) (block 614; par. 28, 29 and 31; Fig. 5 and 6).
Cheng does not explicitly state wherein the width (second width) of the second fin-shaped structure (left side transistor 130) is smaller than the width (first width) of the first fin-shaped structure (right side transistor 160).
In the same field of endeavor, Lilak teaches nanostructure transistors wherein the width (second width) of the second fin-shaped structure (132a of transistors in section 106) is smaller than the width (first width) of the first fin-shaped structure (132b of transistors in section 108) (Fig. 6; steps 605-620).
In the same field of endeavor, Hsu teaches forming nanostructure transistors by depositing, on a substrate (115), a stack (104) comprising a plurality of silicon layers (111) interleaved by a plurality of silicon germanium layers (114) (par. 35); patterning the stack (104) and the substrate (115) into a first fin-shaped structure (left 102) having a first width along a first direction and a second fin-shaped structure (right 102) having a second width along the first direction; wherein the second width is smaller than the first width (Fig. 5A-5C; par. 56 and 57).
It would have been obvious to one having ordinary skill in the art before the invention was effectively filed to utilize the respective widths of the fin-shaped structures as taught by Lilak or Hsu for that of Cheng in order to provide the desired beneficial strain in the channel to improve carrier mobility and transistor performance (‘756; par. 21-26 and 42) or to provide the desired drive current and improve transistor performance (‘478; par. 84).
Referring to Claim 19, as modified above, Cheng in view of Lilak or Hsu teach the limitations of claim 18 but does not explicitly state wherein the first width is between about 14 nm and about 64 nm, wherein the second width is between about 4 nm and about 8 nm, per se.
Lilak teaches that each fin may include a horizontal fin width (dimension in the X-axis direction) in the range of 2-50 nm (or in a subrange of 2-5, 2-10, 5-10, 5-20, 5-30, 5-50, 10-20, 10-30, 10-50, 20-30, 20-50, or 30-50 nm) and/or a maximum horizontal fin width of at most 50, 30, 20, 10, or 5 nm, for example. In some embodiments, the ratio of fin height to fin width may be greater than 1, such as greater than 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9, 10, 15, 20, or greater than any other suitable threshold ratio (par. 71).’
Hsu teaches that the first channel width and the second channel width can be from 5 nm to 100 nm. The first channel width may be 1.5×, 2×, 3×, 4×, 5×, 10×, 20×, or some other multiple of the second channel width (or vice versa). Similarly, the first channel width may differ from the second channel width from 2-10 nm, from 10-20 nm, from 20-50 nm, or from 50-100 nm (par. 56). Hsu also teaches that in some embodiments, each fin may include a horizontal fin width (dimension in the X-axis direction) in the range of 2-50 nm (or in a subrange of 2-5, 2-10, 5-10, 5-20, 5-30, 5-50, 10-20, 10-30, 10-50, 20-30, 20-50, or 30-50 nm) and/or a maximum horizontal fin width of at most 50, 30, 20, 10, or 5 nm, for example. In some embodiments, the ratio of fin height to fin width may be greater than 1, such as greater than 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9, 10, 15, 20, or greater than any other suitable threshold ratio (par. 63).
It would have been obvious to one of ordinary skill in the art before the invention was effectively filed to adjust the respective widths to be in the claimed range in order to provide the desired beneficial strain in the channel to improve carrier mobility and transistor performance (‘756; par. 21-26 and 42) or to provide the desired drive current and improve transistor performance (‘478; par. 84), since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Absent a showing of criticality with respect to respective widths (a result effective variable), it would have been obvious to a person of ordinary skill in the art at the time the invention was effectively filed to adjust the widths through routine experimentation in order to achieve the desired beneficial strain in the channel to improve carrier mobility and transistor performance (‘756; par. 21-26 and 42) or to provide the desired drive current and improve transistor performance (‘478; par. 84). It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Allowable Subject Matter
Claims 1-8 are allowable.
Claims 10 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 1, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device, comprising wherein the first gate dielectric layer merges between two adjacent ones of the first plurality of nanostructures and between a bottommost one of the first plurality of nanostructures and the first base portion in combination with all of the limitations of Claim 1. Claims 2-8 include the limitations of claim 1.
Regarding Claim 10, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device wherein the first gate dielectric layer merges between the first nanostructure and the first base portion in combination with all of the limitations of claims 9 and 10.
Regarding Claim 20, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the method wherein the second gate dielectric layer merges between two adjacent ones of the second nanostructures in combination with all of the limitations of claim 18 and 20.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EARL N TAYLOR whose telephone number is (571)272-8894. The examiner can normally be reached M-F, 9:00am-5:00pm.
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/EARL N TAYLOR/Primary Examiner, Art Unit 2896
EARL N. TAYLOR
Primary Examiner
Art Unit 2896
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