DETAILED ACTION
This action is responsive to the following communications: the Amendment filed on June 16, 2026.
Claims 1-14 are pending. Claims 1 and 3-4 are amended. Claim 1 is independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
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Claims 1-3 and 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Makosiej (US 20230154506) in view of Yu et al. (US 20180090189).
Regarding independent claim 1, Makosiej discloses a static random access memory (SRAM) [see Fig. 5B as well as Fig. 12], comprising:
a first bit line [Fig. 5B: BLT];
a second bit line [Fig. 5B: BLF];
a first precharge circuit [Fig. 5B: 100], comprising:
a first transistor [Fig. 5B: 105], comprising:
a first end coupled to a first reference voltage source [see Fig. 5B, a fourth PMOS transistor (105) is connected between the source terminal of the second PMOS transistor (103) and a supply voltage (VDD), para. 122];
a second end; and
a control end configured to receive a first precharge signal [see Fig. 5B, the precharge signal (NPRE) is connected to the gate terminal of the fourth (105) PMOS transistor, para. 122];
a second transistor [Fig. 5B: 106], comprising:
a first end coupled to the first reference voltage source [see Fig. 5B, a fifth PMOS transistor (106) is connected between the source terminal of the third PMOS transistor (104) and the supply voltage (VDD), para. 122];
a second end; and
a control end configured to receive the first precharge signal [see Fig. 5B, the precharge signal (NPRE) is connected to the gate terminal of the fifth (106) PMOS transistor, para. 122];
a first diode-connected transistor [Fig. 5B: 103], comprising;
a source coupled to the second end of the first transistor [see Fig. 5B, a fourth PMOS transistor (105) is connected between the source terminal of the second PMOS transistor (103) and a supply voltage (VDD), para. 122]; and
a drain, coupled to the first bit line, and configured to output a first precharge voltage [see Fig. 5B, the drain terminal of the second PMOS transistor (103) is connected to the first bit line node (BLT), para. 122];
a gate, coupled to the first bit line [see Fig. 5B, the gate terminal of the second PMOS transistor (103) is connected to the first bit line node (BLT), para. 122];
a second diode-connected transistor [Fig. 5B: 104], comprising;
a source coupled to the second end of the second transistor [see Fig. 5B, a fifth PMOS transistor (106) is connected between the source terminal of the third PMOS transistor (104) and the supply voltage (VDD), para. 122];
a drain, coupled to the second bit line, and configured to output a second precharge voltage [see Fig. 5B, the drain terminal of the third PMOS transistor (104) is connected to the second bit line node (BLF), para. 122]; and
a gate, coupled to the second bit line [see Fig. 5B, the gate terminal of the third PMOS transistor (104) is connected to the second bit line node (BLF), para. 122]; and
a third transistor [Fig. 5B: 102], comprising:
a first end coupled to the drain of the first diode-connected transistor [see Fig. 5B, a connection between the source terminal of the first PMOS transistor (102) and the drain terminal of the second PMOS transistor (103) defines a first bit line node (BLT), para. 122];
a second end coupled to the drain of the second diode-connected transistor [see Fig. 5B, a connection between the drain terminal of the first PMOS transistor (102) and the drain terminal of the third PMOS transistor (104) defines a second bit line node (BLF), para. 122];
and a control end configured to receive the first precharge signal [see Fig. 5B, the precharge signal (NPRE) is connected to the gate terminal of the first (102) PMOS transistors, para. 122]; and
a plurality of SRAM cells, each SRAM cell being coupled between the first bit line and the second bit line [see Fig. 1 with respect to Fig. 5B, precharge circuitry (100) for bit lines (BLT, BLF) of an array of memory cells, para 119];
wherein the first bit line [Fig. 5B: BLT] is configured to receive the first precharge voltage [see Fig. 5B, the drain terminal and the gate terminal of the second PMOS transistor (103) are connected to the first bit line node (BLT), para. 122]; and
wherein the second bit line [Fig. 5B: BLF] is configured to receive the second precharge voltage [see Fig. 5B, the drain terminal and the gate terminal of the third PMOS transistor (104) are connected to the second bit line node (BLF), para. 122].
Furthermore, Makosiej discloses body bias as an available implementation parameter, stating that the precharge implementation can be made in different ways, by connecting the transistors in certain ways and by dimensioning or selecting type of transistors or, if available, by changing the body bias voltage of the precharge transistors [para. 38]. However, Makosiej is silent with respect to disclose the first diode-connected transistor comprising a bulk, coupled to the first bit line and the second diode-connected transistor comprising a bulk, coupled to the second bit line.
Yu et al. teach a static random access memory (SRAM) device [Fig. 5: 200] includes a cross coupled circuit comprising PMOS transistors M1 and M2 [para. 44]. Yu et al. also disclose each PMOS transistor further includes a bulk and the gate terminal is connected to the bulk and has a threshold voltage that varies with a bias voltage applied [para. 44].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Yu et al. to the teaching of Makosiej such that applying the gate coupled to bulk connection as taught by Yu et al. for Makosiej’s diode-connected transistors 103 and 104 as one of the body bias configurations consulted by Makosiej. Because Makosiej already connects the drain and gate of transistor 103 to BLT, connecting its bulk to its gate according to Yu results in the drain, gate and bulk all being coupled to BLT. Similarly, because Makosiej connects the drain and gate of transistor 104 to BLF, applying Yu et al.’s gate coupled to bulk connection results in the drain, gate and bulk all being coupled to BLF.
Regarding claim 2, Makosiej in combination with Yu et al. teach the limitations with respect to claim 1.
Furthermore, Makosiej discloses the first reference voltage source provides an operating voltage, and the first precharge voltage and the second precharge voltage are both less than the operating voltage [the precharge circuitry offers a dynamically reduced precharge voltage on the bit lines by precharging through the precharge circuit with diode connected transistors, para. 38].
Regarding claim 3, Makosiej in combination with Yu et al. teach the limitations with respect to claim 1.
Furthermore, Makosiej in combination with Yu et al. discloses wherein the first diode-connected transistor is a first buck transistor, and the second diode-connected transistor is a second buck transistor [see the rejection of claim 1 above, because Makosiej already connects the drain and gate of transistor 103 to BLT, connecting its bulk to its gate according to Yu results in the drain, gate and bulk all being coupled to BLT. Similarly, because Makosiej connects the drain and gate of transistor 104 to BLF, applying Yu et al.’s gate coupled to bulk connection results in the drain, gate and bulk all being coupled to BLF].
Regarding claim 10, Makosiej in combination with Yu et al. teach the limitations with respect to claim 1.
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Furthermore, Makosiej discloses further comprising:
a word line [Fig. 12: WL]
wherein each SRAM cell [Fig. 12: 300] comprises:
a first inverter [Examiner Markup Makosiej’s Figure 12: INV1];
a second inverter [Examiner Markup Makosiej’s Figure 12: INV2], wherein an input end of the second inverter is coupled to an output end of the first inverter, and an output end of the second inverter is coupled to an input end of the first inverter [see Examiner Markup Makosiej’s Figure 12];
a first switch [Fig. 12: 305], comprising:
a first end coupled to the first bit line [Fig. 12:
B
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];
a second end coupled to the input end of the first inverter and the output end of the second inverter [see Examiner Markup Makosiej’s Figure 12]; and
a control end coupled to the word line [Fig. 12: WL]; and
a second switch [Fig. 12: 306], comprising:
a first end coupled to the second bit line [Fig. 12: BL];
a second end coupled to the output end of the first inverter and the input end of the second inverter [see Examiner Markup Makosiej’s Figure 12]; and
a control end coupled to the word line [Fig. 12: WL].
Regarding claim 11, Makosiej in combination with Yu et al. teach the limitations with respect to claim 10.
Furthermore, Makosiej discloses each SRAM cell is a 6T SRAM cell [see Fig. 12: 6T memory cell (300), para. 128].
Regarding claim 12, Makosiej in combination with Yu et al. teach the limitations with respect to claim 10.
Furthermore, Makosiej discloses the first inverter [Examiner Markup Makosiej’s Figure 12: INV1] comprises:
a first P-type transistor [Fig. 12: 301], comprising:
a first end coupled to the first reference voltage source [Fig. 12: VDD];
a second end coupled to the second end of the first switch [Fig. 12: 305]; and
a control end coupled to the second end of the second switch [Fig. 12: 306]; and
a first N-type transistor [Fig. 1: 302], comprising:
a first end coupled to the second end of the first P-type transistor [Fig. 12: 301];
a second end coupled to a second reference voltage source [see Fig. 12]; and
a control end coupled to the control end of the first P-type transistor [Fig. 12: 301]; and
wherein the second inverter [Examiner Markup Makosiej’s Figure 12: INV2] comprises:
a second P-type transistor [Fig. 12: 303], comprising:
a first end coupled to the first reference voltage source [Fig. 12: VDD];
a second end coupled to the control end of the first P-type transistor [Fig. 12: 301]; and
a control end coupled to the second end of the first switch [Fig. 12: 305]; and
a second N-type transistor [Fig. 12: 304], comprising:
a first end coupled to the control end of the first P-type transistor [Fig. 12: 301];
a second end coupled to the second reference voltage source [see Fig. 12]; and
a control end coupled to the second end of the first P-type transistor [Fig. 12: 301].
Regarding claim 13, Makosiej in combination with Yu et al. teach the limitations with respect to claim 12.
Furthermore, Makosiej discloses the first reference voltage source provides an operating voltage [Fig. 12: VDD], the second reference voltage source provides a ground voltage [see Fig. 12], and the operating voltage is greater than the ground voltage [the first bit line precharge level and the second bit line precharge level relative to a supply voltage (VDD) or ground reference level (GND), para. 40].
Regarding claim 14, Makosiej in combination with Yu et al. teach the limitations with respect to claim 1.
Furthermore, Makosiej discloses the first transistor [Fig. 5B: PMOS transistor (105)], the second transistor [Fig. 5B: PMOS transistor (106)], and the third transistor [Fig. 5B: PMOS transistor (102)] are all P-type transistors [para. 122].
Claims 4-9 are rejected under 35 U.S.C. 103 as being unpatentable over Makosiej (US 20230154506) in view of Yu et al. (US 20180090189) as applied to claim 1 above, and further in view of Keay et al. (US 6314047).
Regarding claim 4, Makosiej in combination with Yu et al. teach the limitation with respect to claim 1.
Furthermore, Makosiej discloses the precharge and limiting unit may, by extension, be configured and applied to any bitcell having a configuration with more than two-bit lines, wherein different bit lines are used depending on the operation. This may include, for example, a two-port 8T bitcell having one read and two read/write bit lines, and a dual-port 8T bitcell having two pairs of read/write bit lines [para. 36].
However, Makosiej is silent with respect to disclose a second precharge circuit (that has the same structure like first precharge circuit);
a third bit line coupled to the drain of the third diode-connected transistor and configured to receive the third precharge voltage; and
a fourth bit line coupled to the drain of the fourth diode-connected transistor and configured to receive the fourth precharge voltage.
Keay et al. teach two different precharge circuit [see Fig. 3: precharge clock A 205 and precharge clock B 206, col. 3, lines 30-55];
a third bit line [Fig. 3: port B bit line 222] coupled to the drain of the third diode-connected transistor and configured to receive the third precharge voltage [see Fig. 3: port B bit line 222 connected to precharge clock B 206]; and
a fourth bit line [Fig. 3: port B bit line 224] coupled to the drain of the fourth diode-connected transistor and configured to receive the fourth precharge voltage [see Fig. 3: port B bit line 224 connected to precharge clock B 206].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Keay et al. to the teaching of Makosiej such that applying the same precharge and limiting unit as taught by Makosiej as applied to claim 1 to the second port’s bit line pair of Keay et al. to obtain the same power stability benefits on both ports and prove cost effective.
Regarding claim 5, Makosiej in combination with Yu et al. and Keay et al. teach the limitation with respect to claim 4.
Furthermore, Makosiej discloses wherein the first reference voltage source is used to provide an operating voltage, and the first precharge voltage, the second precharge voltage, the third precharge voltage, and the fourth precharge voltage are all less than the operating voltage [the precharge circuitry offers a dynamically reduced precharge voltage on the bit lines by precharging through the precharge circuit with diode connected transistors, para. 38].
Regarding claim 6, Makosiej in combination with Yu et al. and Keay et al. teach the limitation with respect to claim 4.
Furthermore, Keay et al. disclose each SRAM cell being coupled between the third bit line and the fourth bit line [see Fig. 3, col. 3, lines 30-55].
Regarding claim 7, Makosiej in combination with Yu et al. and Keay et al. teach the limitation with respect to claim 4.
Furthermore, Keay et al. teach SRAM cell is an 8T SRAM cell [see Fig. 3, a dual port SRAM cell, col. 3, lines 30-55].
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Regarding claim 8, Makosiej in combination with Yu et al. and Keay et al. teach the limitation with respect to claim 4.
Furthermore, Keay et al. teach a static random access memory [Fig. 3] further comprising:
a first word line [Fig. 3: port A word line]; and
a second word line [Fig. 3: port B word line];
wherein each SRAM cell comprises:
a first inverter [Examiner Markup Keay et al.’s Figure 3: INV1];
a second inverter [Examiner Markup Keay et al.’s Figure 3: INV2], wherein an input end of the second inverter is coupled to an output end of the first inverter, and an output end of the second inverter is coupled to an input end of the first inverter [see Examiner Markup Keay et al.’s Figure 3];
a first switch [Fig. 3: 294], comprising:
a first end coupled to the first bit line [Fig. 3: 221];
a second end coupled to the input end of the first inverter [Examiner Markup Keay et al.’s Figure 3: INV1] and the output end of the second inverter [Examiner Markup Keay et al.’s Figure 3: INV2]; and
a control end coupled to the first word line [Fig. 3: port A word line];
a second switch [Fig. 3: 295], comprising:
a first end coupled to the second bit line [Fig. 3: 223];
a second end coupled to the output end of the first inverter [Examiner Markup Keay et al.’s Figure 3: INV1] and the input end of the second inverter [Examiner Markup Keay et al.’s Figure 3: INV2]; and
a control end coupled to the first word line [Fig. 3: port A word line]
a third switch [Fig. 3: 292], comprising:
a first end coupled to the third bit line [Fig. 3: 222];
a second end coupled to the input end of the first inverter [Examiner Markup Keay et al.’s Figure 3: INV1] and the output end of the second inverter [Examiner Markup Keay et al.’s Figure 3: INV2]; and
a control end coupled to the second word line [Fig. 3: port B word line]; and
a fourth switch [Fig. 3: 293], comprising:
a first end coupled to the fourth bit line [Fig. 3: 224];
a second end coupled to the output end of the first inverter [Examiner Markup Keay et al.’s Figure 3: INV1] and the input end of the second inverter [Examiner Markup Keay et al.’s Figure 3: INV2]; and
a control end coupled to the second word line [Fig. 3: port B word line].
Regarding claim 9, Makosiej in combination with Yu et al. and Keay et al. teach the limitation with respect to claim 8.
Furthermore, Keay et al. disclose the first inverter [Examiner Markup Keay et al.’s Figure 3: INV1] comprises:
a first P-type transistor [Fig. 3: 270], comprising:
a first end coupled to the first reference voltage source [Fig. 3: VDD];
a second end coupled to the second end of the first switch [Fig. 3: 294] and the second end of the third switch [Fig. 3: 292]; and
a control end coupled to the second end of the second switch [Fig. 3: 295] and the second end of the fourth switch [Fig. 17: MN11]; and
a first N-type transistor [Fig. 3: 290], comprising:
a first end coupled to the second end of the first P-type transistor [Fig. 3: 270];
a second end coupled to a second reference voltage source [Fig. 3: GND]; and
a control end coupled to the control end of the first P-type transistor [Fig. 3: 270]; and
wherein the second inverter [Examiner Markup Keay et al.’s Figure 3: INV2] comprises:
a second P-type transistor [Fig. 3: 271], comprising:
a first end coupled to the first reference voltage source [Fig. 3: VDD];
a second end coupled to the control end of the first P-type transistor [Fig. 3: 270]; and
a control end coupled to the second end of the first switch [Fig. 3: 294] and the second end of the third switch [Fig. 3: 292]; and
a second N-type transistor [Fig. 3: 291], comprising:
a first end coupled to the control end of the first P-type transistor [Fig. 3: 270];
a second end coupled to the second reference voltage source [Fig. 3: GND]; and
a control end coupled to the second end of the first P-type transistor [Fig. 3: 270].
Response to Arguments
Applicant’s arguments with respect to claims 1-14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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/DUY H LUONG/Examiner, Art Unit 2825
/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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