DETAILED ACTION
This action is responsive to the following communications: the Amendment filed on December 8, 2025 and the Foreign Priority papers retrieved on January 16, 2024
Claims 1-14 are pending. Claims 1 is independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2 and 4-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Independent claim 1 recites “an equivalent diode.” This term is not defined in applicant’s originally filed disclosure and has no reasonably certain boundaries.
By using the adjective “equivalent” to modify the term “diode,” by ordinary interpretation convention, excludes a diode because a diode is not an “equivalent diode”---a diode is a diode. To determine the full scope of what makes a circuit element or elements an “equivalent” diode requires clear guidance in applicant’s originally filed disclosure. Applicant’s originally filed disclosure is not only the single best source, but also usually the dispositive source, to resolve the meaning of a claim term. Vitronics Corp. v. Conceptronic, Inc., 90 F.3d 1576, 1582 (Fed. Cir. 1996). Applicant’s originally filed disclosure provides only one example of this “equivalent diode” as a diode-connected transistor (i.e., Fig. 3: Qa, which has its gate and one of its Source/Drain commonly connected to the same node).
Therefore, the claimed “equivalent diode” can only mean the diode-connected transistor, and nothing more. By using a broader term that does not have clear boundaries, the claim term creates a zone of uncertainty as to the scope of an “equivalent” diode. See Nautilus, Inc. v. Biosig Instruments, Inc., 572 U.S. 898, 910 (2014).
Claim 3 is not rejected as indefinite because it defines the “equivalent diode” as the transistor that is connected in the way one of ordinary skill in the art would recognize as “diode-connected.”
Dependent claims 2, 4-14, however, do not resolve this indefiniteness.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 10-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Makosiej (US 20230154506).
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Regarding independent claim 1, Makosiej discloses a static random access memory (SRAM) [see Fig. 5B as well as Fig. 12], comprising:
a first precharge circuit [Fig. 5B: 100], comprising:
a first transistor [Fig. 5B: 105], comprising:
a first end coupled to a first reference voltage source [see Fig. 5B, a fourth PMOS transistor (105) is connected between the source terminal of the second PMOS transistor (103) and a supply voltage (VDD), para. 122];
a second end; and
a control end configured to receive a first precharge signal [see Fig. 5B, the precharge signal (NPRE) is connected to the gate terminal of the fourth (105) PMOS transistor, para. 122];
a second transistor [Fig. 5B: 106], comprising:
a first end coupled to the first reference voltage source [see Fig. 5B, a fifth PMOS transistor (106) is connected between the source terminal of the third PMOS transistor (104) and the supply voltage (VDD), para. 122];
a second end; and
a control end configured to receive the first precharge signal [see Fig. 5B, the precharge signal (NPRE) is connected to the gate terminal of the fifth (106) PMOS transistor, para. 122];
a first equivalent diode [Fig. 5B: 103], comprising;
an anode coupled to the second end of the first transistor [see Fig. 5B, a fourth PMOS transistor (105) is connected between the source terminal of the second PMOS transistor (103) and a supply voltage (VDD), para. 122]; and
a cathode configured to output a first precharge voltage [see Fig. 5B, the drain terminal and the gate terminal of the second PMOS transistor (103) are connected to the first bit line node (BLT), para. 122];
a second equivalent diode [Fig. 5B: 104], comprising;
an anode coupled to the second end of the second transistor [see Fig. 5B, a fifth PMOS transistor (106) is connected between the source terminal of the third PMOS transistor (104) and the supply voltage (VDD), para. 122]; and
a cathode configured to output a second precharge voltage [see Fig. 5B, the drain terminal and the gate terminal of the third PMOS transistor (104) are connected to the second bit line node (BLF), para. 122]; and
a third transistor [Fig. 5B: 102], comprising:
a first end coupled to the cathode of the first equivalent diode [see Fig. 5B, a connection between the source terminal of the first PMOS transistor (102) and the drain terminal of the second PMOS transistor (103) defines a first bit line node (BLT), para. 122];
a second end coupled to the cathode of the second equivalent diode [see Fig. 5B, a connection between the drain terminal of the first PMOS transistor (102) and the drain terminal of the third PMOS transistor (104) defines a second bit line node (BLF), para. 122];
and a control end configured to receive the first precharge signal [see Fig. 5B, the precharge signal (NPRE) is connected to the gate terminal of the first (102) PMOS transistors, para. 122];
a first bit line [Fig. 5B: BLT] coupled to the cathode of the first equivalent diode [Fig. 5B: 103] and configured to receive the first precharge voltage [see Fig. 5B, the drain terminal and the gate terminal of the second PMOS transistor (103) are connected to the first bit line node (BLT), para. 122];
a second bit line [Fig. 5B: BLF] coupled to the cathode of the second equivalent diode [Fig. 5B: 104] and configured to receive the second precharge voltage [see Fig. 5B, the drain terminal and the gate terminal of the third PMOS transistor (104) are connected to the second bit line node (BLF), para. 122]; and
a plurality of SRAM cells, each SRAM cell being coupled between the first bit line and the second bit line [see Fig. 1 with respect to Fig. 5B, precharge circuitry (100) for bit lines (BLT, BLF) of an array of memory cells, para 119].
Regarding claim 2, Makosiej discloses the first reference voltage source provides an operating voltage, and the first precharge voltage and the second precharge voltage are both less than the operating voltage [the precharge circuitry offers a dynamically reduced precharge voltage on the bit lines by precharging through the precharge circuit with diode connected transistors, para. 38].
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Regarding claim 10, Makosiej discloses further comprising:
a word line [Fig. 12: WL]
wherein each SRAM cell [Fig. 12: 300] comprises:
a first inverter [Examiner Markup Makosiej’s Figure 12: INV1];
a second inverter [Examiner Markup Makosiej’s Figure 12: INV2], wherein an input end of the second inverter is coupled to an output end of the first inverter, and an output end of the second inverter is coupled to an input end of the first inverter [see Examiner Markup Makosiej’s Figure 12];
a first switch [Fig. 12: 305], comprising:
a first end coupled to the first bit line [Fig. 12:
B
L
-
];
a second end coupled to the input end of the first inverter and the output end of the second inverter [see Examiner Markup Makosiej’s Figure 12]; and
a control end coupled to the word line [Fig. 12: WL]; and
a second switch [Fig. 12: 306], comprising:
a first end coupled to the second bit line [Fig. 12: BL];
a second end coupled to the output end of the first inverter and the input end of the second inverter [see Examiner Markup Makosiej’s Figure 12]; and
a control end coupled to the word line [Fig. 12: WL].
Regarding claim 11, Makosiej discloses each SRAM cell is a 6T SRAM cell [see Fig. 12: 6T memory cell (300), para. 128].
Regarding claim 12, Makosiej discloses the first inverter [Examiner Markup Makosiej’s Figure 12: INV1] comprises:
a first P-type transistor [Fig. 12: 301], comprising:
a first end coupled to the first reference voltage source [Fig. 12: VDD];
a second end coupled to the second end of the first switch [Fig. 12: 305]; and
a control end coupled to the second end of the second switch [Fig. 12: 306]; and
a first N-type transistor [Fig. 1: 302], comprising:
a first end coupled to the second end of the first P-type transistor [Fig. 12: 301];
a second end coupled to a second reference voltage source [see Fig. 12]; and
a control end coupled to the control end of the first P-type transistor [Fig. 12: 301]; and
wherein the second inverter [Examiner Markup Makosiej’s Figure 12: INV2] comprises:
a second P-type transistor [Fig. 12: 303], comprising:
a first end coupled to the first reference voltage source [Fig. 12: VDD];
a second end coupled to the control end of the first P-type transistor [Fig. 12: 301]; and
a control end coupled to the second end of the first switch [Fig. 12: 305]; and
a second N-type transistor [Fig. 12: 304], comprising:
a first end coupled to the control end of the first P-type transistor [Fig. 12: 301];
a second end coupled to the second reference voltage source [see Fig. 12]; and
a control end coupled to the second end of the first P-type transistor [Fig. 12: 301].
Regarding claim 13, Makosiej discloses the first reference voltage source provides an operating voltage [Fig. 12: VDD], the second reference voltage source provides a ground voltage [see Fig. 12], and the operating voltage is greater than the ground voltage [the first bit line precharge level and the second bit line precharge level relative to a supply voltage (VDD) or ground reference level (GND), para. 40].
Regarding claim 14, Makosiej discloses the first transistor [Fig. 5B: PMOS transistor (105)], the second transistor [Fig. 5B: PMOS transistor (106)], and the third transistor [Fig. 5B: PMOS transistor (102)] are all P-type transistors [para. 122].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Makosiej (US 20230154506) as applied to claim 1 above, in view of Stuber et al. (US 20110012669).
Regarding claim 3, Makosiej teaches the limitation with respect to claim 1.
Furthermore, Makosiej discloses the first equivalent diode [Fig. 5B: 103] further comprises a first buck transistor, and a drain and a gate of the first buck transistor are coupled to the first bit line [see Fig. 5B, the drain terminal and the gate terminal of the second PMOS transistor (103) are connected to the first bit line node (BLT), para. 122]; and
wherein the second equivalent diode [Fig. 9: 104] further comprises a second buck transistor, and a drain and a gate of the second buck transistor are coupled to the second bit line [see Fig. 5B, the drain terminal and the gate terminal of the third PMOS transistor (104) are connected to the second bit line node (BLF), para. 122].
However, Makosiej is silent with respect to a bulk of the first buck transistor are coupled to the first bit line and a bulk of the second buck transistor are coupled to the second bit line.
Stuber et al. teach a buck transistor [Fig. 2: 203] where the gate [Fig. 2: 113] is connected to the body [Fig. 2: 109, the transistor that includes body contact 204 and second contact 205 connects gate 113 to body 109, para. 26].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Stuber et al. to the teaching of Makosiej such that adopting the gate-body tie as taught by Stuber et al. on the equivalent diodes of Makosiej to provide higher threshold voltage when the transistor is biased in the OFF condition and lower threshold voltage when the device is in the ON condition [see Stuber et al.’s para. 26].
Claims 4-9 are rejected under 35 U.S.C. 103 as being unpatentable over Makosiej (US 20230154506) as applied to claim 1 above, in view of Keay et al. (US 6314047).
Regarding claim 4, Makosiej teaches the limitation with respect to claim 1.
Furthermore, Makosiej discloses the precharge and limiting unit may, by extension, be configured and applied to any bitcell having a configuration with more than two-bit lines, wherein different bit lines are used depending on the operation. This may include, for example, a two-port 8T bitcell having one read and two read/write bit lines, and a dual-port 8T bitcell having two pairs of read/write bit lines [para. 36].
However, Makosiej is silent with respect to disclose a second precharge circuit (that has the same structure like first precharge circuit);
a third bit line coupled to the cathode of the third equivalent diode and configured to receive the third precharge voltage; and
a fourth bit line coupled to the cathode of the fourth equivalent diode and configured to receive the fourth precharge voltage.
Keay et al. teach two different precharge circuit [see Fig. 3: precharge clock A 205 and precharge clock B 206, col. 3, lines 30-55];
a third bit line [Fig. 3: port B bit line 222] coupled to the cathode of the third equivalent diode and configured to receive the third precharge voltage [see Fig. 3: port B bit line 222 connected to precharge clock B 206]; and
a fourth bit line [Fig. 3: port B bit line 224] coupled to the cathode of the fourth equivalent diode and configured to receive the fourth precharge voltage [see Fig. 3: port B bit line 224 connected to precharge clock B 206].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Keay et al. to the teaching of Makosiej such that applying the same precharge and limiting unit as taught by Makosiej as applied to claim 1 to the second port’s bit line pair of Keay et al. to obtain the same power stability benefits on both ports and prove cost effective.
Regarding claim 5, Makosiej in combination with Keay et al. teach the limitation with respect to claim 4.
Furthermore, Makosiej disclose wherein the first reference voltage source is used to provide an operating voltage, and the first precharge voltage, the second precharge voltage, the third precharge voltage, and the fourth precharge voltage are all less than the operating voltage [the precharge circuitry offers a dynamically reduced precharge voltage on the bit lines by precharging through the precharge circuit with diode connected transistors, para. 38].
Regarding claim 6, Makosiej in combination with Keay et al. teach the limitation with respect to claim 4.
Furthermore, Watanabe et al. disclose each SRAM cell being coupled between the third bit line and the fourth bit line [see Fig. 3, col. 3, lines 30-55].
Regarding claim 7, Makosiej in combination with Keay et al. teach the limitation with respect to claim 4.
Furthermore, Keay et al. teach SRAM cell is an 8T SRAM cell [see Fig. 3, a dual port SRAM cell, col. 3, lines 30-55].
Regarding claim 8, Makosiej in combination with Keay et al. teach the limitation with respect to claim 4.
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Furthermore, Keay et al. teach a static random access memory [Fig. 3] further comprising:
a first word line [Fig. 3: port A word line]; and
a second word line [Fig. 3: port B word line];
wherein each SRAM cell comprises:
a first inverter [Examiner Markup Keay et al.’s Figure 3: INV1];
a second inverter [Examiner Markup Keay et al.’s Figure 3: INV2], wherein an input end of the second inverter is coupled to an output end of the first inverter, and an output end of the second inverter is coupled to an input end of the first inverter [see Examiner Markup Keay et al.’s Figure 3];
a first switch [Fig. 3: 294], comprising:
a first end coupled to the first bit line [Fig. 3: 221];
a second end coupled to the input end of the first inverter [Examiner Markup Keay et al.’s Figure 3: INV1] and the output end of the second inverter [Examiner Markup Keay et al.’s Figure 3: INV2]; and
a control end coupled to the first word line [Fig. 3: port A word line];
a second switch [Fig. 3: 295], comprising:
a first end coupled to the second bit line [Fig. 3: 223];
a second end coupled to the output end of the first inverter [Examiner Markup Keay et al.’s Figure 3: INV1] and the input end of the second inverter [Examiner Markup Keay et al.’s Figure 3: INV2]; and
a control end coupled to the first word line [Fig. 3: port A word line]
a third switch [Fig. 3: 292], comprising:
a first end coupled to the third bit line [Fig. 3: 222];
a second end coupled to the input end of the first inverter [Examiner Markup Keay et al.’s Figure 3: INV1] and the output end of the second inverter [Examiner Markup Keay et al.’s Figure 3: INV2]; and
a control end coupled to the second word line [Fig. 3: port B word line]; and
a fourth switch [Fig. 3: 293], comprising:
a first end coupled to the fourth bit line [Fig. 3: 224];
a second end coupled to the output end of the first inverter [Examiner Markup Keay et al.’s Figure 3: INV1] and the input end of the second inverter [Examiner Markup Keay et al.’s Figure 3: INV2]; and
a control end coupled to the second word line [Fig. 3: port B word line].
Regarding claim 9, Makosiej in combination with Keay et al. teach the limitation with respect to claim 4.
Furthermore, Keay et al. disclose the first inverter [Examiner Markup Keay et al.’s Figure 3: INV1] comprises:
a first P-type transistor [Fig. 3: 270], comprising:
a first end coupled to the first reference voltage source [Fig. 3: VDD];
a second end coupled to the second end of the first switch [Fig. 3: 294] and the second end of the third switch [Fig. 3: 292]; and
a control end coupled to the second end of the second switch [Fig. 3: 295] and the second end of the fourth switch [Fig. 17: MN11]; and
a first N-type transistor [Fig. 3: 290], comprising:
a first end coupled to the second end of the first P-type transistor [Fig. 3: 270];
a second end coupled to a second reference voltage source [Fig. 3: GND]; and
a control end coupled to the control end of the first P-type transistor [Fig. 3: 270]; and
wherein the second inverter [Examiner Markup Keay et al.’s Figure 3: INV2] comprises:
a second P-type transistor [Fig. 3: 271], comprising:
a first end coupled to the first reference voltage source [Fig. 3: VDD];
a second end coupled to the control end of the first P-type transistor [Fig. 3: 270]; and
a control end coupled to the second end of the first switch [Fig. 3: 294] and the second end of the third switch [Fig. 3: 292]; and
a second N-type transistor [Fig. 3: 291], comprising:
a first end coupled to the control end of the first P-type transistor [Fig. 3: 270];
a second end coupled to the second reference voltage source [Fig. 3: GND]; and
a control end coupled to the second end of the first P-type transistor [Fig. 3: 270].
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at (571)272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825