Prosecution Insights
Last updated: October 01, 2026
Application No. 18/581,339

SILICON CARBIDE POWER DEVICES HAVING EXPANDED CREEPAGE DISTANCES

Non-Final OA §102§103
Filed
Feb 19, 2024
Examiner
TORNOW, MARK W
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Wolfspeed Inc.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
582 granted / 752 resolved
+9.4% vs TC avg
Moderate +13% lift
Without
With
+13.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
14 currently pending
Career history
770
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
45.9%
+5.9% vs TC avg
§102
26.7%
-13.3% vs TC avg
§112
21.3%
-18.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 752 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of Invention I, Claims 1-13 and 15-20 in the reply filed on 6/22/26 is acknowledged. The traversal is on the ground(s) that the inventions are not independent and distinct and there is no serious burden. This is not found persuasive because 1) Applicant's argument is that 35 U.S.C. 121 requires that distinct (related) inventions also be shown to be independent (unrelated) inventions, as well. Applicant is invited to demonstrate the merits of this argument by providing an example of two distinct (related) inventions that could also be viewed as being independent (unrelated). Because Applicant has not disputed the accuracy of the Examiner's finding of distinct inventions, the restriction is still deemed to be appropriate, and is therefore maintained and 2) as noted in the restriction requirement on page 2, the inventions require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search queries) and the prior art applicable to one invention would not likely be applicable to the other invention, which constitutes a serious search and/or examination burden. The requirement is still deemed proper and is therefore made FINAL. Information Disclosure Statement The information disclosure statement (IDS) submitted on 6/26/25 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 2, and 4-7 are rejected under 35 U.S.C. 102(a)(1) as being antcipated by Tokumitsu et al. (US Patent Application Publication No. 2022/0199786) (“Tokumitsu”). Regarding Claim 1, Tokumitsu teaches a semiconductor device, comprising: a drift region (¶0034) an active region (Figure 2, item 5), including at least one active element therein (¶0034), and an edge termination region (Figure 2, item 4) around at least a portion of a perimeter of the active region when viewed in plan view (see Figure 1); and a passivation structure (Figure 2, item 8+11+10) on the edge termination region, the passivation structure comprising: an insulating layer (Figure 2, item 8, ¶0035) on the drift region; and a first polymer layer (Figure 2, item 10, ¶0035) on the insulating layer opposite the drift region, wherein the first polymer layer comprises a top surface that is nonplanar (see Figure 2, note shape depicted of item 10). Regarding Claim 2, Tonkumitsu further teaches the first polymer layer (Figure 2, item 10) is configured to extend horizontally, parallel to a top surface of the drift region, from a peripheral edge of the edge termination region toward the active region over a majority of the edge termination region (see Figure 2, note coverage of item 10 over item 4). Regarding Claim 4, Tonkumitsu further teaches the first polymer layer comprises a polyimide (¶0038). Regarding Claim 5, Tonkumitsu further teaches the insulating layer comprises an oxide (¶0037). Regarding Claim 6, Tonkumitsu further teaches the top surface of the first polymer layer comprises one or more openings extending vertically, perpendicular to the top surface of the drift region, at least partially into the first polymer layer (see Figure 2, note shape depicted of item 10). Regarding Claim 7, Tonkumitsu further teaches the first polymer layer comprises a first end and a second end opposite the first end, the first end of the first polymer layer is vertically coplanar with a peripheral edge of the edge termination region (see Figure 2, note right edge of item 10), and the second end of the first polymer layer is over a top surface of a source electrode of a metal- oxide-semiconductor field-effect transistor in the active region (see Figure 3, note left edge of item 10 overlapping item 14 which extends into the active region). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Tonkumitsu as applied to Claim 1 above, and further in view of Richmond et al. (US Patent Application Publication No. 2022/0178979)(“Richmond”). Regarding Claim 3, Tonkumitsu teaches Claim 1 as indicated above. Tonkumitsu does not specifically teach the first polymer layer is configured to extend horizontally, parallel to a top surface of the drift region, from a peripheral edge of the edge termination, across the top surface of the insulating layer, and partially into the active region. However, Richmond teaches a polymer protection layer (Figure 2, item 28) over a termination region (Figure 2, item 14) that also extends over the active region (Figure 2, item 12). It would have been obvious to a person having ordinary skill in the art at the time of effective filing to use the additional protection taught by Richmond in the device on Tonkumitsu, if the additional protection of the active area from scratches was desired (see Richmond, ¶0033). Additionally, a change in shape of an element was considered a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration was significant (In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (MPEP §2144.04) Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Tonkumitsu as applied to Claim 1 above, and further in view of Konrath et al. (US Patent Application Publication No. 2015/0255362)(“Konrath”). Regarding Claim 11, Tonkumitsu teaches Claim 1 as indicated above. Tonkumitsu does not specifically teach a mold compound on a peripheral edge of the edge termination region, the mold compound extending around the semiconductor device when viewed in plan view. However, Konrath teaches including a mold compound (Figure 5, item 61, ¶0040) on a peripheral edge of a termination region, extending around a semiconductor device (see Figure 5, item 61 wrapping around the edge of 100). It would have been obvious to a person having ordinary skill in the art at the time of effective filing to use the mold compound of Konrath in the device of Tonkumitsu, as doing so would allow for protection of the device from outside environmental or electrical influence. Regarding Claim 12, Konrath further teaches a top surface of the mold compound is coplanar with the top surface of the first polymer layer (see Figure 5 – note the term “a top surface of the mold compound” and “the top surface of the first polymer layer” do not require “top surface” to refer to the “uppermost surface” – thus the top surface exists for element so long as it can be considered “top” relative to a different surface of the element). Regarding Claim 13, Konrath further teaches at least one of a top surface, a side surface and a bottom surface of the mold compound comprises at least one trench therein extending at least partially into the mold compound (see Figure 5, note bottom surface of 61 has a “trench” where 100 is located). Claims 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Tonkumitsu in view of Konrath. Regarding Claim 15, Tonkumitsu teaches a semiconductor device, comprising: a drift region (¶0034) an active region (Figure 2, item 5) comprising a portion of the drift region, and an edge termination region (Figure 2, item 4) in the drift region around at least a portion of a perimeter of the active region when viewed in plan view (see Figure 1); and a passivation structure (Figure 2, item 8+11+10) on the edge termination region, the passivation structure comprising: an insulating layer (Figure 2, item 8, ¶0035) on the drift region; and a first polymer layer (Figure 2, item 10, ¶0035) on the insulating layer opposite the drift region. Tonkumitsu does not specifically teach a mold compound on a peripheral edge of the edge termination region, wherein the mold compound does not extend over a top surface of the active region. However, Konrath teaches including a mold compound (Figure 5, item 61, ¶0040) on a peripheral edge of a termination region, extending around a semiconductor device (see Figure 5, item 61 wrapping around the edge of 100) but does not extend over the active region (see Figure 5). It would have been obvious to a person having ordinary skill in the art at the time of effective filing to use the mold compound of Konrath in the device of Tonkumitsu, as doing so would allow for protection of the device from outside environmental or electrical influence. Regarding Claim 16, Tonkumitsu further teaches the top surface of the first polymer is substantially planar (see section of 10 that is substantially planar – note the language does not require the entire uppermost surface of the layer to be planar). Regarding Claim 17, Konrath further teaches at least one of the top surface, a side surface and a bottom surface of the mold compound comprises at least one trench therein (see Figure 5, note bottom surface of 61 has a “trench” where 100 is located). Regarding Claim 18, Konrath further teaches the mold compound extends around the peripheral edge of the edge termination region when viewed in plan view (see Figure 5, note location of item 61 relative to item 100). Regarding Claim 19, Tonkumitsu further teaches the top surface of the first polymer layer has a nonplanar cross-sectional profile (see item 10). Allowable Subject Matter Claims 8-10 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: None of the prior art, alone or in combination, teaches “a second polymer layer between the insulating layer and the first polymer layer” of Claim 8 or “includes at least one metal oxide semiconductor field effect transistor (MOSFET), the semiconductor device further comprising a second polymer layer on the first polymer layer and the mold compound, the second polymer layer extending horizontally from an outer edge of the mold compound, opposite the peripheral edge of the edge termination region, to a top surface of a source electrode of the MOSFET in the active region” of Claim 20. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Uchida et al. (US Patent Application Publication No. 2020/0266268) Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK W TORNOW whose telephone number is (571)270-7534. The examiner can normally be reached M-Th 6:30-4:30 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. MARK W. TORNOW Primary Examiner Art Unit 2891 /MARK W TORNOW/Primary Examiner, Art Unit 2891
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Prosecution Timeline

Feb 19, 2024
Application Filed
Sep 16, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
90%
With Interview (+13.0%)
2y 10m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 752 resolved cases by this examiner. Grant probability derived from career allowance rate.

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