DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the second recess and related steps of claim 13 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2.20.2024 is being considered by the examiner.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: the claims use language not found in the specification but are supported by the specification unless rejected below for failing to comply with the written description requirement.
For example, from claims 1, 7 and 15, the first/second transistors, the first/second dielectric layers, the first/second cap layers, the third dielectric layer, the first/second etchings, the first recess and/or expanding of the first recess are supported by the specification, satisfying the written description requirement, but do not have proper antecedent basis.
Revision of all claims is required to ensure the claimed subject matter has proper antecedent basis.
Claim Objections
Claim 14 is objected to because of the following informalities: “The method of claim 7, thinning the first contact, wherein after thinning the upper surface of the second gate structure is free of the first contact” should read – The method of claim 7, further comprising thinning the first contact, wherein after said thinning, the upper surface of the second gate structure is free of the first contact-- or similar. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 13 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 13, the formation of the second recess and related steps are not supported by the specification as filed. Figs. 4(A)-10(B) and related text disclose the formation of a first recess but not of a second recess as claimed.
Original claims are subject to the written description requirement and claim 13 fails it since there is no disclosure of the second recess and related steps as claimed.
Claim Rejections - 35 USC § 102 and - 35 USC § 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 11-12, 15-16 and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al. (US 20140349476 A1).
Regarding claim 1, Chen discloses a method of forming a semiconductor device, the method comprising:
forming a first transistor (second one left to right in Fig. 4A) on a substrate (10), the first transistor comprising a first source/drain region (14/15), a first gate structure (12), a first dielectric layer (18/20) along a sidewall of the first gate structure, and a first cap layer (24) over the first gate structure (Fig. 4);
forming a second transistor (third one left to right in Fig. 4A) on the substrate, the second transistor comprising a second source/drain region (14/15), a second gate structure (12), a second dielectric layer (18/20) along a sidewall of the second gate structure, and a second cap layer (24) over the second gate structure (Fig. 4);
forming a third dielectric layer (22) on the substrate between the first dielectric layer and the second dielectric layer (Fig. 4);
performing a first etching process (Figs. 6-8) to remove a portion of the third dielectric layer to form a first recess (42, second left to right in Fig. 5A), the first recess exposing the first source/drain region;
after performing the first etching process (Figs. 6-8), performing a second etching process (Figs. 10-11) to expand the first recess (now 42+44) by removing (partly) the second dielectric layer along the sidewall of the second gate structure, wherein after performing the second etching process, the first recess exposes (by 44) at least an exposed portion of an upper surface of the second gate structure; and
forming a first contact (54/56) in the first recess, the first contact contacting the first source/drain region (Fig. 12).
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Regarding claim 2, Chen discloses the method of claim 1, wherein performing the second etching process (Figs. 10-11) removes a portion of the second cap layer (24).
Regarding claim 3, Chen discloses the method of claim 1, wherein performing the second etching process (Figs. 10-11) recesses the upper surface (Fig. 11) of the second gate structure (12).
Regarding claim 4, Chen discloses the method of claim 1, wherein the first dielectric layer (18/20) isolates the first contact (54/56) from the first gate structure (12, Fig. 12).
Regarding claim 5, Chen discloses the method of claim 1, wherein, after forming the first contact, an upper(most) surface of the second cap layer is level with an upper (not uppermost) surface of the first contact (Fig. 12).
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Regarding claim 6, Chen discloses the method of claim 1, wherein the first contact (54/56) contacts a sidewall of the second dielectric layer (18/20, Fig. 12).
Regarding claim 7, Chen discloses a method of forming a semiconductor device, the method comprising:
forming a first transistor on a substrate (10), the first transistor comprising a first source/drain region (14/15), a first gate structure (12), a first dielectric layer (18/20) along a sidewall of the first gate structure, and a first cap layer (24) over the first gate structure (Fig. 4);
forming a second transistor on the substrate, the second transistor comprising a second source/drain region (14/15), a second gate structure (12), a second dielectric layer (18/20) along a sidewall of the second gate structure, and a second cap layer (24) over the second gate structure, wherein the second gate structure is adjacent the first source/drain region (Fig. 4);
forming a third dielectric layer (22) on the substrate between the first dielectric layer and the second dielectric layer (Fig. 4);
performing a first etching process (Figs. 6-8) to remove a portion of the third dielectric layer to form a first recess (42), the first recess exposing the first source/drain region, the first dielectric layer and the second dielectric layer (Fig. 8);
after performing the first etching process, performing a second etching process (Figs. 9-11) to expand the first recess (creating 42+44) by removing a portion of the second dielectric layer along the sidewall of the second gate structure and to remove a portion of the second cap layer (Fig. 11), wherein after performing the second etching process, the first recess (not 42+44) exposes (partly at least) at least an upper surface of the second gate structure and the sidewall of the second gate structure (Fig. 11); and
forming a first contact (54/56) in the first recess, the first contact contacting the first source/drain region, the sidewall of the second gate structure, and the upper surface of the second gate structure (Fig. 12).
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Regarding claim 8, Chen discloses the method of claim 7, wherein performing the second etching process (ending in Fig. 11) recesses the upper surface of the second gate structure (12) to form a second recess (44) in the upper surface of the second gate structure, wherein forming the first contact comprises forming the first contact in the second recess (Fig. 12).
Regarding claim 9, Chen discloses the method of claim 7, wherein the first contact (54/56) contacts (indirectly at least) the sidewall of the second gate structure (12) from the upper surface of the second gate structure to a lower (not lowermost) surface of the second gate structure (Fig. 12).
Regarding claim 11, Chen discloses the method of claim 7, wherein the second dielectric layer (18/20) extends partially between the first contact and the second gate structure (Fig. 12).
Regarding claim 12, Chen discloses the method of claim 7, wherein an upper (not uppermost) surface of the first contact is level with an upper(most) surface of the first cap layer (Fig. 12).
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Regarding claim 15, Chen discloses a method of forming a semiconductor device, the method comprising:
forming a first transistor on a substrate (10), the first transistor comprising a first source/drain region (14/15), a first gate structure (12), a first dielectric layer (18/20) along a sidewall of the first gate structure, and a first cap layer (24) over the first gate structure (Fig. 4);
forming a second transistor on the substrate, the second transistor comprising a second source/drain region (14/15), a second gate structure (12), a second dielectric layer (18/20) along a sidewall of the second gate structure, and a second cap layer (24) over the second gate structure, wherein the second gate structure is adjacent the first source/drain region (Fig. 4); forming a third dielectric layer (22) on the substrate between the first dielectric layer and the second dielectric layer (Fig. 4);
performing a first etching process (Figs. 6-8) to remove a portion of the third dielectric layer to expose the first source/drain region, the first dielectric layer and the second dielectric layer (Fig. 8);
after performing the first etching process, performing a second etching process (ending with Fig. 11) to remove a portion of the second dielectric layer (18/19) to expose (partly at least) the sidewall of the second gate structure and to remove a portion (creating 44) of the second cap layer to expose an upper surface of the second gate structure (Fig. 11); and
forming a first contact (54/56) on the first source/drain region, the sidewall of the second gate structure, and the upper surface of the second gate structure (Fig. 12).
Regarding claim 16, Chen discloses the method of claim 15, wherein the second etching process forms a recess (44) in the upper surface of the second gate structure (Fig. 11).
Regarding claim 18, Chen discloses the method of claim 15, wherein the first contact (54/56) physically (and indirectly at least) contacts an entire height of the sidewall of the second gate structure in a cross-sectional view (Fig. 12).
Regarding claim 19, Chen discloses the method of claim 15, wherein the second dielectric layer (18/20) extends between a portion of the first contact and the second gate structure (Fig. 12).
Regarding claim 20, Chen discloses the method of claim 15, wherein a width (width of 54) of the first contact over the second gate structure (12) is less than a width (width of 56) of the first contact over the first source/drain region (Fig. 12).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20140349476 A1).
Regarding claim 10, Chen fails to disclose the method of claim 7, wherein the first contact has a “T” shape in a plan view.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at the claimed shape in Chen because such modification would have involved a mere change in size/shape of a component and it has been held that a change in size/shape is generally recognized as being within the level of ordinary skill in the art. See MPEP 2144.04 IV. Furthermore, said shape would be obvious so as to ensure the gate is electrically contacted while preventing unwanted shorting of nearby structures.
Allowable Subject Matter
Claims 14 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record fails to disclose or suggest (claim 14) the method of claim 7, thinning the first contact, wherein after thinning the upper surface of the second gate structure is free of the first contact and (claim 17) The method of claim 16, further comprising performing a thinning process, the thinning process removing the second cap layer from over the second gate structure, wherein after performing the thinning process an upper surface of the first contact is level with and the upper surface of the second gate structure.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Regarding claim 1, Oosuka et al. (US 20090108379 A1) discloses a method of forming a semiconductor device, the method comprising:
forming a first transistor on a substrate (11), the first transistor comprising a first source/drain region (29A), a first gate structure (22), a first dielectric layer (23 or parts thereof) along a sidewall of the first gate structure (Fig. 2A),
forming a second transistor on the substrate, the second transistor comprising
forming a third dielectric layer (81) on the substrate between the first dielectric layer and the second dielectric layer (Fig. 2B);
performing a first
after performing the first
forming a first contact (61/67) in the first recess, the first contact contacting the first source/drain region (Fig. 4A).
Regarding claim 7, Oosuka et al. (US 20090108379 A1) discloses a method of forming a semiconductor device, the method comprising:
forming a first transistor on a substrate (11), the first transistor comprising a first source/drain region (29A), a first gate structure (22), a first dielectric layer (23 or parts thereof) along a sidewall of the first gate structure (Fig. 2A),
forming a second transistor on the substrate, the second transistor comprising
forming a third dielectric layer (81) on the substrate between the first dielectric layer and the second dielectric layer (Fig. 2B);
performing a first
after performing the first
forming a first contact (61/67) in the first recess, the first contact contacting the first source/drain region, the sidewall of the second gate structure, and the upper surface of the second gate structure (Fig. 4A).
Regarding claim 15, Oosuka et al. (US 20090108379 A1) a method of forming a semiconductor device, the method comprising:
forming a first transistor on a substrate (11), the first transistor comprising a first source/drain region (29A), a first gate structure (22), a first dielectric layer (23 or parts thereof) along a sidewall of the first gate structure (Fig. 2A)
forming a second transistor on the substrate, the second transistor comprising thereof) along a sidewall of the second gate structure (Fig. 2A),
forming a third dielectric layer (81) on the substrate between the first dielectric layer and the second dielectric layer (Fig. 2B);
performing a first
after performing the first
forming a first contact (61/67) on the first source/drain region, the sidewall of the second gate structure, and the upper surface of the second gate structure (Fig. 4A).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/Primary Examiner, Art Unit 2818
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