Prosecution Insights
Last updated: July 17, 2026
Application No. 18/581,728

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Non-Final OA §102§103§112
Filed
Feb 20, 2024
Priority
May 30, 2018 — CN 201810538418.6 +1 more
Examiner
LI, MEIYA
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Silergy Semiconductor Technology (Hangzhou) Ltd.
OA Round
1 (Non-Final)
69%
Grant Probability
Favorable
1-2
OA Rounds
1y 2m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 69% — above average
69%
Career Allowance Rate
641 granted / 931 resolved
+0.9% vs TC avg
Strong +26% interview lift
Without
With
+25.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
50 currently pending
Career history
982
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
65.6%
+25.6% vs TC avg
§102
15.9%
-24.1% vs TC avg
§112
15.3%
-24.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 931 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of species I, claims 1-16, in the reply filed on May 12, 2026 is acknowledged. The traversal is on the ground(s) that “the species are not patentably distinct and that no serious search burden has been adequately demonstrated”. This is not found persuasive because 1) the Examiner failed to identify with any specificity the alleged patentably distinct species and 2) the Office failed to adequately explain why a serious burden would be placed on the Examiner if restriction is not required. This is not found persuasive because regarding the term "independent and distinct" as used in 35 USC 121, MPEP section 802.01 clearly indicates that restriction between distinct inventions may be proper even if they are dependent (or related), and, regarding the search burden, as indicated in the restriction requirement mailed to applicant on March 26, 2026, serious search burden of both distinct, yet dependent, inventions was established due to the different search strategies and different search queries that would be required; the prior art applicable to one invention would not likely be applicable to another invention. The requirement is still deemed proper and is therefore made FINAL. Claim 10 has been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species. There is no support in the elected embodiment of Figs. 3A-3I for the claim limitations of wherein the first and second well regions are formed simultaneously”, as recited in claim 10, lines 3-4, and this feature is found on unelected embodiment of Figs. 5A-5I. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on February 20, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Objections Claims 11-16 are objected to because of the following informalities: “incontact” should read “in contact” (claim 11, line 17). Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 11-16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. There is no support in the original specification (in the prior-filed application #16/416,420, filed on May 20, 2019) for the claim limitations of “forming a substrate having a first doping type …”, as recited in claim 10. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 6, 8, 9 and 11-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claimed limitations of “sidewall spacers on surfaces of both sidewalls of the gate conductor”, as recited in claim 6, are unclear as to whether said limitations are in one-to-one, multiple-to-one or one-to-multiple relationship between “sidewall spacer” and “surface” and in one-to-one or multiple-to-one between “surface” and “sidewall applicant refers. The claimed limitation of “a second doping type”, as recited in claim 8, is unclear as to whether said limitation is the same as or different from “a second doping type”, as recited in claim 1. The claimed limitations of “a high-voltage side device” and “a low-voltage side device”, as recited in claim 11, lines 3-4, is unclear as to whether said limitation is the same as or different from “a semiconductor device”, as recited in claim 10, line 1. The claimed limitation of “the LDMOS transistor comprising a high-voltage side device and a low-voltage side device”, as recited in claim 11, is unclear as to how a single transistor can comprise multiple devices. Claim 11 recites the limitation “the surface of the substrate” in line 8. There is insufficient antecedent basis for this limitation in the claim. Claim 11 recites the limitation “the side” in line 10. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different from “a first side” and/or “a second side”, as recited in claim 11, lines 6 and 7. The claimed limitation of “opposite sides”, as recited in claim 11, line 11, is unclear as to whether said limitation is the same as or different from “a first side” and/or “a second side”, as recited in claim 11, lines 6 and 7. The claimed limitation of “a first region”, as recited in claims 11 (line 18) and 12-14, is unclear as to whether said limitation is the same as or different from “a first region”, as recited in claim 11, lines 11-12. The claimed limitation of “a gate structure”, as recited in claim 16, is unclear as to whether said limitation is the same as or different from “a gate oxide layer”, as recited in claim 11. The claimed limitation of “a surface of the substrate”, as recited in claim 16, is unclear as to whether said limitation is the same as or different from “the surface of the substrate”, as recited in claim 11. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-6, as best understood, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kikuchi et al. (6,897,525). As for claim 1, Kikuchi et al. show in Figs. 1, 2A-5B and related text a method of manufacturing a semiconductor device having a laterally diffused metal oxide semiconductor (LDMOS) transistor A, the method comprising: a) forming a first deep well region 21 having a first doping type P in a substrate 1 having the first doping type (Fig. 2A; Col. 8, lines 12); b) forming a drift region 22 having a second doping type N and being located in the first deep well region (Figs. 2B), and c) forming a drain region 5B having the second doping type and being located in the drift region (Fig. 5B), wherein the second doping type is opposite to the first doping type, d) wherein a doping concentration peak of the first deep well region is located below the drift region to optimize the breakdown voltage and on-resistance of the LDMOS transistor. The limitation “a doping concentration peak of the first deep well region is located below the drift region to optimize the breakdown voltage and on-resistance of the LDMOS transistor” has not been given patentable weight because it is considered to be intended use and/or functional language. This type of description does not affect the structure of the final device. It is respectfully noted that intended use and/or other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In a claim drawn to a process of making, the intended use must result in a manipulative difference as compared to the prior art. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). Note that Applicant has burden of proof in such cases, as the above case law makes clear. Furthermore, it has been held that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). As for claim 2, Kikuchi et al. show before the forming the drain region, forming a body region 3 having the first doping type in the first deep well region (Fig. 4A). As for claim 3, Kikuchi et al. show forming a source region having the second doping type and a body contact region 12 having the first doping type in the body region (Figs. 4B-5B). As for claim 4, Kikuchi et al. show before the forming the drain region, forming a gate structure 9/6/7/43 on a surface of the substrate, wherein at least a portion of the first deep well region is located below the gate structure between the source region and the drain region (Figs. 2A-5A). As for claim 5, Kikuchi et al. show the forming the gate structure comprises: a) forming a high-voltage drain oxide layer 9 on a surface of the drift region (Fig. 2A); b) forming a gate oxide layer 6 on the surface of the substrate, wherein the gate oxide layer is in contact with the high-voltage drain oxide layer (Fig. 3B); and c) forming a gate conductor 7 on the high-voltage drain oxide layer and the gate oxide layer (Fig. 3B), wherein the gate conductor is located between the source region and the drain region (Fig. 5A). As for claim 6, Kikuchi et al. show the forming the gate structure further comprises forming sidewall spacers 43 on surfaces of both sidewalls of the gate conductor (Fig. 5A). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 11-16, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al. (2014/0024186) in view of Chen et al. (2005/0073007). As for claim 11, Yoo et al. show in Figs. 3A-3H and related text a method of manufacturing a semiconductor device 300 having a laterally diffused metal oxide semiconductor (LDMOS) transistor 301, the laterally diffused metal oxide semiconductor (LDMOS) transistor comprising a high-voltage side device 301 and a low-voltage side device 302, the method comprising: a) forming a substrate 20 having a first doping type and being shared by both the high-voltage side device located at a first side HV of the substrate, and the low-voltage side device located at a second side LV of the substrate (Fig. 3A); b) forming a gate oxide layer 30 located on the surface of the substrate and being shared by both the high-voltage side device and the low-voltage side device (Fig. 3E); and d) forming a source region 46A and a drain region 46A located in a first region HV, wherein the source region has the second doping type N, and the drain region has the second doping type N. Yoo et al. do not disclose c) forming a first well region located in the substrate of the side and having a second doping type, wherein the first well region is located at opposite sides of a first region of the substrate; and e) forming a buried layer having the second doping type located in the first side of the substrate, wherein the buried layer is in contact with the first well region to form a first region that is surrounded by the buried layer and the first well region. Chen et al. teach in Figs. 5-15 and related text c) forming a first well region 232 located in the substrate 202 of the side and having a second doping type N, wherein the first well region is located at opposite sides of a first region 226 of the substrate (Fig. 7); and e) forming a buried layer 204 having the second doping type located in the first side of the substrate, wherein the buried layer is in contact with the first well region to form a first region that is surrounded by the buried layer and the first well region (Figs. 5-7). Yoo et al. and Chen et al. are analogous art because they are directed to a method of manufacturing a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yoo et al. with the specified feature(s) of Chen et al. because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to form a first well region located in the substrate of the side and having a second doping type, wherein the first well region being located at opposite sides of a first region of the substrate; and form a buried layer having the second doping type located in the first side of the substrate, wherein the buried layer being in contact with the first well region to form a first region that is surrounded by the buried layer and the first well region, as taught by Chen et al., in Yoo et al.'s device, in order to reduce leakage current and improve the performance of the device. As for claim 12, the combined device shows forming a drift region 41 located in the first region and having the second doping type ([0041]), wherein the drain region is located in the drift region (Yoo: Figs. 3E-3F). As for claim 13, the combined device shows forming a body region 48A located in the first region and having the first doping type ([0051]), wherein the source region is located in the body region (Yoo: Figs. 3G-3H). As for claim 14, the combined device shows forming a first deep well region 31 located in the first region and having the first doping type ([0038]), wherein the drift region and the body region are located in the first deep well region (Fig. 3A, 3H). As for claim 15, the combined device shows a doping concentration peak of the first deep well region is located below the drift region (Yoo: Figs. 3A). As for claim 16, the combined device shows forming a gate structure 44A/45A/42 located on a surface of the substrate, wherein at least a portion of the first deep well region is located below the gate structure between the source region and the drain region (Yoo: Fig. 3H). Allowable Subject Matter Claims 7-9 are allowed. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or suggest, singularly or in combination, at least the limitations of “after the forming the drift region, forming a buried layer having the second doping type in the substrate, wherein the buried layer is located below the first deep well region”, as recited in claim 7. Claims 7-9 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEIYA LI whose telephone number is (571)270-1572. The examiner can normally be reached Monday-Friday 7AM-3PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LYNNE GURLEY can be reached at (571)272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MEIYA LI/Primary Examiner, Art Unit 2811
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Prosecution Timeline

Feb 20, 2024
Application Filed
Jun 17, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
69%
Grant Probability
94%
With Interview (+25.5%)
3y 7m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 931 resolved cases by this examiner. Grant probability derived from career allowance rate.

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