DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/5/2026was filed after the mailing date of the non-final rejection on 5/29/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Status
Previous action: claims 1 through 12 rejected
Present action: claims 1 through 13 rejected
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 1, 2, 3, 4, 5, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuang (US 2015/0108644) in view of Siping (CN11069020, machine translation)
Regarding claim 1.
Kuang teaches:
A semiconductor device structure (fig 11:300; [para 0029]), comprising: a first substrate (fig 11:102; [para 0010]);
a passivation layer (fig 11:118; [para 0015]) disposed over the first substrate (fig 11:102; [para 0010]);
an interlayer dielectric (fig 11:116; [para 0015]) disposed between the first substrate (fig 11:102; [para 0010]) and the passivation layer (fig 11:118; [para 0015]);
a conductive line (fig 11:112; [para 0014]) between the passivation layer (fig 11:118; [para 0015]) and the first substrate (fig 11:102; [para 0010]);
a dielectric structure (fig 11:120,220; [para 0027]) disposed over the passivation layer (fig 11:118; [para 0015]);
a first conductive layer (fig 11:130; [para 0027]) electrically connected to the conductive line (fig 11:112; [para 0014]);
and a second conductive layer (fig 11:230; [para 0027]) disposed over the first conductive layer (fig 11:130; [para 0027])and electrically connected to the conductive line (fig 11:112; [para 0014]) through the first conductive layer (fig 11:130; [para 0027]), wherein the first conductive layer (fig 11:130; [para 0027]) is extended from the interlayer dielectric (fig 11:116; [para 0015]) to the dielectric structure (fig 11:120,220; [para 0027]) through the passivation layer (fig 11:118; [para 0015]), such that the first conductive layer (fig 11:130; [para 0027]) penetrates through the passivation layer (fig 11:118; [para 0015]) into the dielectric structure (fig 11:120,220; [para 0027]);
wherein the dielectric structure (fig 11:120,220; [para 0027]) laterally overlapping the first conductive layer (fig 11:130; [para 0027]) .
Kuang does not teach an air gap.
Siping teaches:
the dielectric structure (fig 1:14,24; [page 12]) defines an air gap (fig 1:13,23; [page 10,12]) laterally overlapping the first conductive layer (fig 1:211,221; [page 12]) and spaced apart from the first conductive layer (fig 1:211,221; [page 12]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an air gap adjacent the conductive structure in order to reduce parasitic capacitance and current leakage (page 8).
Regarding claim 2.
Kuang in view of Siping teaches the semiconductor device structure of claim 1, further
Siping teaches:
the air gap (fig 1:13,23; [page 10,12]) laterally overlaps the second conductive layer (fig 1:121,111; [page 9,12]) and is spaced apart from the second conductive layer (fig 1:121,111; [page 9,12]).
Regarding claim 3.
Kuang in view of Siping teaches the semiconductor device structure of claim 1, further,
Kuang teaches:
the dielectric structure (fig 11:120,220; [para 0027])comprises a first dielectric layer (fig 11:120; [para 0027])disposed on the passivation layer (fig 11:118; [para 0015]) and a second dielectric layer (fig 11:220; [para 0027]) disposed on the first dielectric layer (fig 11:120; [para 0027]), .
Siping teaches:
a height of the air gap (fig 1:13,23; [page 10,12]) is equal to an overall thickness of the first dielectric layer (fig 1:24; [page 12]) and the second dielectric layer (fig 1:14; [page 12]).
Regarding claim 4.
Kuang in view of Siping teaches the semiconductor device structure of claim 3, further,
Kuang teaches
wherein a sidewall of the first conductive layer (fig 11:130; [para 0027]) continuously extends from the first dielectric layer (fig 11:120; [para 0027]) of the dielectric structure (fig 11:120,220; [para 0027]) to the passivation layer (fig 11:118; [para 0015]).
Regarding claim 5.
Kuang in view of Siping teaches the semiconductor device structure of claim 1, further,
Kuang teaches
a vertical dimension of the first conductive layer (fig 11:130; [para 0027]) is greater than a horizontal dimension of the first conductive layer (fig 11:130; [para 0027]).
Regarding claim 9.
Kuang in view of Siping teaches the semiconductor device structure of claim 1, furter,
Kuang teaches:
wherein a material (porous dielectric; [para 0015]) of the passivation layer (fig 11:118; [para 0015]) is different from a material (silicon nitride; [para 0017]) of the dielectric structure (fig 11:120,220; [para 0027]).
Claim(s) 6, 7, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuang (US 2015/0108644) in view of Siping (CN11069020, machine translation) as applied to claim 1, and further in view of Mrozek (US 2024/0387419)
Regarding claim 6.
Kuang in view of Siping teaches the semiconductor device structure of claim 1, above.
Kuang in view of Siping does not teach the first conductive layer is tapered toward the first substrate.
Mrozek teaches:
the first conductive layer (fig 3:18; [para 0032]) is tapered toward the first substrate (fig 3:10; [para 0032]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to taper the conductive layer toward the substrate so that the width of the pad can be adjusted during the polishing process (paragraph 38).
Regarding claim 7.
Kuang in view of Siping in view of Mrozek teaches the semiconductor device structure of claim 6, further,
Siping teaches:
a second substrate (fig 1:1; [page 9,12]) disposed over the second conductive layer (fig 1:121,111; [page 9,12]);
wherein the air gap (fig 1:13,23; [page 10,12]) is enclosed by the second substrate (fig 1:1; [page 9,12]).
Mrozek teaches:
a second substrate (fig 3:20; [para 0043])disposed over the second conductive layer (fig 3:28; [para 0043]), wherein the second conductive layer (fig 3:28; [para 0043]) is tapered toward the second substrate (fig 3:20; [para 0043]);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to taper the conductive layer toward the substrate so that the width of the pad can be adjusted during the polishing process (paragraph 38).
Regarding claim 8.
Kuang in view of Siping in view of Mrozek teaches the semiconductor device structure of claim 7, further,
Kuang teaches:
the second substrate (fig 11:202,204; [para 0024]) comprises a semiconductor substrate (; [para 0010,0024]).
Siping teaches:
the second substrate (fig 1:1; [page 9]) comprises a semiconductor substrate (; [page 9]).
Claim(s) 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuang (US 2015/0108644) in view of Siping (CN11069020, machine translation) as applied to claim 3, and further in view of Katkar (US 2019/0109042)
Regarding claim 10.
Kuang in view of Siping teaches the semiconductor device structure of claim 3, further,
Kuang teaches:
the passivation layer (fig 11:118; [para 0015]) , , the first dielectric layer (fig 11:120; [para 0027]).
Siping teaches:
the air gap (fig 1:13,23; [page 10,12]) comprises a first terminal portion and a neck portion in communication with the first terminal portion, and an aperture of the first terminal portion is different from an aperture of the neck portion, wherein the first terminal portion is formed through the first dielectric layer (fig 1:24; [page 12]).
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Kunag in view of Siping does not teach an aperture of the first terminal portion is different from an aperture of the neck portion
Katkar teaches:
the air gap (fig 3a:302; [para 0042]) comprises a first terminal portion and a neck portion in communication with the first terminal portion, and an aperture of the first terminal portion is different from an aperture of the neck portion, wherein the first terminal portion is formed through the first dielectric layer (fig 3a:102; [para 0042]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a neck portion having a different aperture than the terminal portions in order to account for the accuracy limitations of device placement stemming from pick-and-place tools, contact grid patterns on the die or wafer surfaces, or dissimilar pad sizes that result in partial overlay and misalignment (paragraph 5).
Regarding claim 11
Kunag in view of Siping in view of Katkar teaches the semiconductor device structure of claim 10, further
Siping teaches:
the air gap (fig 1:13,23; [page 10,12]) further comprises a second terminal portion in communication with the neck portion (fig 1 annotated above), wherein the second terminal portion is formed through the second dielectric layer (fig 1:14; [page 12]).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuang (US 2015/0108644) in view of Siping (CN11069020, machine translation) as applied to claim 1, and further in view of Katkar (US 2019/0109042)
Regarding claim 12.
Kuang in view of Siping teaches the semiconductor device structure of claim 1, above
Kuang in view of Siping does not teach the first conductive layer is partially misaligned with the second conductive layer.
Katkar teaches:
the first conductive layer (fig 3a:106; [para 0040]) is partially misaligned (fig 3a:306; [para 0045]) with the second conductive layer (fig 3a:108; [para 0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the first conductive layer to be partially misaligned with the second conductive layer due to the accuracy limitations of device placement resulting from pick-and-place tools, contact grid patterns on the die or wafer surfaces, or dissimilar pad sizes that result in partial overlay and misalignment (paragraph 5).
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Newly applied prior art Kuang (US 2015/0108644) in view of Siping (CN11069020, machine translation) reads on the claims of the application.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/ Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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