DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1, Embodiment I (Fig. 1A), Sub-species C (Figs. 1A, 1E), claims 1-10, in the reply filed on June 17, 2026 is acknowledged. Action on the merits is as follows:
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,610,531. Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim 1-10 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of copending Application No. 18/428,127. Although the claims at issue are not identical, they are not patentably distinct from each other.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Shih et al. (Shih) (US 2024/0315011 A1).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
In regards to claims 1-10, Shih (Figs. 1A, 1B and associated text) discloses the Applicant’s claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (Jeon) (US 2023/0061185 A1) in view of Cho et al. (Cho) (US 2022/0013525 A1).
In regard to claim 1, Jeon (Figs. 10-12 and associated text) discloses a semiconductor device (Fig. 12), comprising: a substrate (item 200); a channel structure (item 430) disposed on the substrate (item 200); a first word line (item 440, paragraphs 67, 157) disposed on the substrate (item 200) and surrounding the channel structure (item 430); a dielectric layer (item 412) disposed over the substrate (item 200); and a trench capacitor (item 480) disposed on the channel structure (item 430), opposite to the substrate (item 200), wherein the trench capacitor (item 480) comprises a first conductive layer (item 481 or 483) and a second conductive layer (item 483 or 485) and a first dielectric layer (item 482) and a second dielectric layer (item 484), but does not specifically disclose wherein the channel structure tapers along a first direction away from the trench capacitor.
Cho (Fig. 26 and associated text) discloses wherein the channel structure (item 310) tapers along a first direction (D3) away from the trench capacitor (item 350).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teaching of Cho, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regard to claim 2, Jeon (Figs. 10-12 and associated text) discloses further comprising a first bit line (item 420) disposed between the channel structure (item 430) and the substrate (item 200).
In regards to claim 3, Jeon (Figs. 10-12 and associated text) as modified by Cho does not specifically disclose further comprising a first landing pad (LP) disposed between the channel structure and the first bit line.
However, in another embodiment of Jeong (paragraphs 45-50) discloses comprising a first landing pad (LP) (item LP) disposed between the channel structure and the first bit line.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings from other embodiments of Jeon for the purpose of increasing the contact area via the introduction of the landing pad LP which may allow a contact resistance between the active area ACT and the lower electrode of the capacitor to be reduced (paragraph 48).
In regards to claim 4, Jeon (Figs. 10-12 and associated text) as modified by Cho does not specifically disclose further comprising a second landing pad (LP) (item LP) disposed between the trench capacitor and the channel structure.
However, in another embodiment of Jeong (paragraphs 45-50) discloses comprising a first landing pad (LP) (item LP) disposed between the trench capacitor and the channel structure.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings from other embodiments of Jeon for the purpose of increasing the contact area via the introduction of the landing pad LP which may allow a contact resistance between the active area ACT and the lower electrode of the capacitor to be reduced (paragraph 48).
In regards to claim 5, Jeon as modified by Cho (Fig. 26 and associated text) discloses further comprising: a third conductive layer (item 414) disposed on the substrate (item 100); a first contact (item 412) disposed on and electrically connected to the third conductive layer (item 414), wherein the first contact (item 412) is a monolithic structure; and a second contact (another one of item 412) disposed between the first word line (item 220) and the third conductive layer (item 414), wherein the first word line (item 220) is electrically connected to the first contact (item 412) through the second contact (another one of item 412) and the third conductive layer (item 414).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Cho for the purpose of an electrical connection.
In regards to claim 6, Jeon (Figs. 10-12 and associated text) discloses further comprising: a polysilicon layer (item 460, paragraph 165) disposed on the trench capacitor (item 480) opposite to the channel structure, wherein the polysilicon layer (item 460) has a curved sidewall; and a fourth conductive layer (item 481) disposed on the polysilicon layer (item 460), wherein the fourth conductive layer (item 481) has a sidewall, and wherein the curved sidewall of the polysilicon layer (item 460) is recessed from the sidewall of the fourth conductive layer (item 481).
In regards to claim 7, Jeon (Figs. 10-12 and associated text) discloses wherein the first conductive layer (item 481 or 483) disposed within the trench capacitor (item 480) and covers a sidewall of the dielectric layer (item 412).
In regards to claim 8, Jeon (Figs. 10-12 and associated text) discloses wherein the first dielectric layer (item 482) is disposed over a top surface of the dielectric layer (item 412) and covers the dielectric layer (item 412) and the first conductive layer (items 481 or 483).
In regards to claim 9, Jeon (Figs. 10-12 and associated text) discloses wherein the second dielectric layer (item 484) is disposed over the dielectric layer (item 412) and is disposed on a trench corner of the trenches and partially covers a top surface and a sidewall of the dielectric layer (item 412).
In regards to claim 10, Jeon (Figs. 10-12 and associated text) discloses wherein the second conductive layer (items 483 or 485) is disposed over the dielectric layer (item 412) and covers the first conductive layer (item 481 or 483), the first dielectric layer (item 482) and the second dielectric layer (item 484).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. All references listed in the 892 that were published in 2023 and assigned to Yangtze Memory could have been used as primary references. These references disclose all the limitations except for the trench capacitor including a first conductive layer, a second conductive layer, a first dielectric layer, a second dielectric layer and a tapering channel structure. These deficiencies could be remedied by Jeon and Cho above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 July 7, 2026
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