Prosecution Insights
Last updated: July 17, 2026
Application No. 18/581,806

SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §102§103
Filed
Feb 20, 2024
Priority
Feb 02, 2024 — divisional of 18/430,890
Examiner
ABDELAZIEZ, YASSER A
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
NANYA TECHNOLOGY Corporation
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
703 granted / 816 resolved
+18.2% vs TC avg
Minimal +3% lift
Without
With
+2.7%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
29 currently pending
Career history
843
Total Applications
across all art units

Statute-Specific Performance

§101
2.2%
-37.8% vs TC avg
§103
73.2%
+33.2% vs TC avg
§102
12.9%
-27.1% vs TC avg
§112
10.5%
-29.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 816 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant election of species I, reading on Claims 1-13 without traverse is acknowledged. Claims 1-13 are examined on the merit. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 7, 8, 12 and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YANG (US 2021/0265475), (hereinafter, YANG). RE Claims 1, TANG discloses in FIGS. 1-21 a semiconductor device and a method of making the same. TANG discloses a method of manufacturing a semiconductor structure, comprising: providing a substrate having an array region 103 and a periphery region 105, referring to FIG. 5; forming a first opening 515 and a second opening 517 in the array region and the periphery region, respectively, referring to FIG. 7; forming a third opening 517 through the second opening 517, referring to FIG. 13; and forming a first buried gate structure 207/205/203 and a second buried gate structure 307/305/303, wherein the first buried gate structure 207/205/203 is formed in the first opening 515, and the second buried gate structure 307/305/303 is formed in the second opening and the third opening 517, referring to FIG. 13. RE Claims 7, TANG discloses a method, wherein a depth of the second buried gate structure 307/305/303 is greater than a depth of the first buried gate structure 207/205/203, referring to FIGS. 7 and 13. RE Claims 8, TANG discloses a method, wherein a width of the second buried gate structure 307/305/303 is greater than a width of the first buried gate structure 207/205/203, referring to FIGS. 7 and 13. RE Claims 12, TANG discloses a method, wherein forming the first buried gate structure 207/205/203 and the second buried gate structure 307/305/303 comprises: forming a first gate dielectric layer “gate insulating material” lining 519 the first opening and a second gate dielectric layer 519 “gate insulating material” lining the second opening and the third opening 517; forming a first gate electrode 523 in the first opening 515 and a second gate electrode 523 in the second opening 517 and the third opening 517; and forming a first capping layer 209 over the first gate electrode 207 and a second capping layer 309 over the second gate electrode 307. RE Claims 13, TANG discloses a method, wherein the first gate electrode 207 and the first capping layer 209 are separated from the substrate 101 by the first gate dielectric layer 519/203, and the second gate electrode 307 and the second capping layer 309 are separated from the substrate 101 by the second gate dielectric layer 519/303, referring to FIG.15. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or non-obviousness. Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over YANG (US 2021/0265475), (hereinafter, YANG). RE Claims 2, TANG does not explicitly disclose a method, further comprising: forming a plurality of metal lines, wherein the metal lines are formed over the substrate. However, Examiner takes an Official Notice that metal lines are formed over the substrate is well-known in art. Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application to form metal lines over the substrate in order to connect to the buried gate to external and internal circuitry as a well-known interconnect structure in integrated circuits structure. Allowable Subject Matter Claims 3-6 and 9-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Feb 20, 2024
Application Filed
Jul 07, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
89%
With Interview (+2.7%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 816 resolved cases by this examiner. Grant probability derived from career allowance rate.

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