Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a Final office action based on application 18/582,016 in response to reply filed April 27, 2026. Claims 1-25 are currently pending and have been considered below.
Claim Rejections - 35 USC § 112
Claim 1 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the second conductive layer" in line 17. There is insufficient antecedent basis for this limitation in the claim as there is no mention of a first conductive layer to distinguish between a first and second conductive layer and it is unclear if the “second conductive layer” is the same as “a conductive layer” in line 16.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (Chinese Publication CN 115863310) in view of Foo (Pre-Grant Publication 2024/0063148) and Chen (Pre-Grant Publication 2025/0132296).
Regarding claim 1 & 6, Li discloses a semiconductor device comprising:
a first substrate (Fig. 1, 103);
a first semiconductor die (101) disposed over the first substrate;
a second semiconductor die (102) disposed over the first substrate;
an interconnect bridge (104) disposed over the first semiconductor die and second semiconductor die, wherein the interconnect bridge includes, a second substrate and can be an integrated passive substrate (Paragraph [0074]);
an encapsulant (112) deposited over the first substrate, first semiconductor die, second semiconductor die, and interconnect bridge.
Li does not explicitly disclose the interconnection bridge includes a conductive trace formed over a first surface of the second substrate and electrically coupled from the first semiconductor die to the second semiconductor die, a conductive via formed through the second substrate, and an integrated passive device (IPD) formed over a second surface of the second substrate and electrically coupled to the first semiconductor die or second semiconductor die through the conductive via. However Foo discloses a semiconductor device comprising:
An interconnect bridge (Fig. 1) including a conductive trace (130; Paragraph [0036) formed on a first surface of a bridge substrate (102) and electrically coupled dies (Fig. 2, 252/254) wherein a conductive layer (114) is deposited over a second surface of the substrate and patterned to form an integrated passive device such as a capacitor formed by layers (116/118/114) and electrically connected to the dies (252/254).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the interconnect bridge including a passive device and conductive traces on surfaces of a substrate because it will form a bridge capable of enabling shorter decoupling capacitance connection and improve power integrity of a multi-chip package (Paragraph [0014]).
Further Chen discloses a semiconductor device comprising:
A bridge die (Fig. 2d, 140) having one or more passive devices such as a capacitor (145) within a substrate (141-1) and having conductive via (143) formed through the substrate electrically coupling the passive device to first and second dies (170a/170c).
It would have been obvious to those having ordinary skill in the art at the time of invention to form conductive via through the substrate of the interconnect bridge because it will establish an electrical pathway between the dies and the passive as well as establish shorter electrical pathways for faster signal transmission between components of the package.
Regarding claim 2, Li, Foo, and Chen disclose all of the limitations of claim 1 (addressed above). Chen further discloses:
The interconnect bridge (140) can be bonded to dies (270a/270b) by hybrid/direct bonding (Fig. 3a-3f).
It would have been obvious to those having ordinary skill in the art at the time of invention to hybrid bond the interconnect bridge to the first and second die because it will establish shorter signal paths between the dies and the interconnect bridge thereby improving signal/power integrity (Paragraph [0053]).
Regarding claim 3, Li further discloses:
a first solder bump (105; Paragraph [0080 & 0082]) disposed between the first semiconductor die and interconnect bridge; and
a second solder bump (105; Paragraph [0080 & 0082]) disposed between the second semiconductor die and interconnect bridge.
Regarding claim 4, Li further discloses:
a third solder bump (105/106) disposed between the interconnect bridge and first substrate.
Regarding claim 5, Li further discloses:
the second substrate comprises a high-resistivity silicon (HRS) substrate (Paragraph [0074]).
Regarding claim 7 & 10-12, Li discloses a semiconductor device comprising:
a first semiconductor die (101);
a second semiconductor die (102); and
an interconnect bridge (104) disposed over the first semiconductor die and second semiconductor die, wherein the interconnect bridge includes, a silicon substrate and can be an integrated passive substrate (Paragraph [0074]).
Li does not explicitly disclose the interconnection bridge includes a conductive trace formed over a first surface of the second substrate and electrically coupled from the first semiconductor die to the second semiconductor die, a conductive via formed through the second substrate, and an integrated passive device (IPD) formed over a second surface of the second substrate and electrically coupled to the first semiconductor die or second semiconductor die through the conductive via. However Foo discloses a semiconductor device comprising:
An interconnect bridge (Fig. 1) including a conductive trace (130; Paragraph [0036) formed on a first surface of a bridge substrate (102) and electrically coupled dies (Fig. 2, 252/254) wherein an integrated passive device such as a capacitor formed by layers (116/118/114) is formed over a second surface of the substrate and electrically connected to the dies (252/254).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the interconnect bridge including a passive device and conductive traces on surfaces of a substrate because it will form a bridge capable of enabling shorter decoupling capacitance connection and improve power integrity of a multi-chip package (Paragraph [0014]).
Further Chen discloses a semiconductor device comprising:
A bridge die (Fig. 2d, 140) having one or more passive devices such as a capacitor (145) within a substrate (141-1) and having conductive via (143) formed through the substrate electrically coupling the passive device to first and second dies (170a/170c).
It would have been obvious to those having ordinary skill in the art at the time of invention to form conductive via through the substrate of the interconnect bridge because it will establish an electrical pathway between the dies and the passive as well as establish shorter electrical pathways for faster signal transmission between components of the package.
Regarding claim 8, Li, Foo, and Chen disclose all of the limitations of claim 7 (addressed above). Chen further discloses:
The interconnect bridge (140) can be bonded to dies (270a/270b) by hybrid/direct bonding (Fig. 3a-3f).
It would have been obvious to those having ordinary skill in the art at the time of invention to hybrid bond the interconnect bridge to the first and second die because it will establish shorter signal paths between the dies and the interconnect bridge thereby improving signal/power integrity (Paragraph [0053]).
Regarding claim 9, Li further discloses:
a first solder bump (105; Paragraph [0080 & 0082]) disposed between the first semiconductor die and interconnect bridge; and
a second solder bump (105; Paragraph [0080 & 0082]) disposed between the second semiconductor die and interconnect bridge.
Regarding claim 13, Li further discloses:
A bond wire (109) extending from the first semiconductor die.
Regarding claim 14 & 16-18, Li discloses a semiconductor device comprising:
providing a first semiconductor die (101);
disposing a second semiconductor die (102) adjacent to the first semiconductor die;
forming an interconnect bridge (104) by, providing a silicon substrate and an integrated passive substrate (Paragraph [0074]), and
disposing the interconnect bridge over the first semiconductor die and second semiconductor die (Fig. 1).
Li does not explicitly disclose the interconnection bridge includes a conductive trace formed over a second surface of the second substrate and electrically coupled from the first semiconductor die to the second semiconductor die, a conductive via formed through the second substrate, and an integrated passive device (IPD) formed over a first surface of the second substrate and electrically coupled to the first semiconductor die or second semiconductor die through the conductive via. However Foo discloses a semiconductor device comprising:
An interconnect bridge (Fig. 1) including a conductive trace (130; Paragraph [0036) formed on a second surface of a bridge substrate (102) and electrically coupled dies (Fig. 2, 252/254) wherein a conductive layer (114) is deposited over a first surface of the substrate and patterned to form an integrated passive device such as a capacitor formed by layers (116/118/114) and electrically connected to the dies (252/254).
Second conductive traces (122/124) formed over the surface where the capacitor is formed.
It would have been obvious to those having ordinary skill in the art at the time of invention to form the interconnect bridge including a passive device and conductive traces on surfaces of a substrate because it will form a bridge capable of enabling shorter decoupling capacitance connection and improve power integrity of a multi-chip package (Paragraph [0014]).
Further Chen discloses a semiconductor device comprising:
A bridge die (Fig. 2d, 140) having one or more passive devices such as a capacitor (145) within a substrate (141-1) and having conductive via (143) formed through the substrate electrically coupling the passive device to first and second dies (170a/170c).
It would have been obvious to those having ordinary skill in the art at the time of invention to form conductive via through the substrate of the interconnect bridge because it will establish an electrical pathway between the dies and the passive as well as establish shorter electrical pathways for faster signal transmission between components of the package.
Regarding claim 15, Li, Foo, and Chen disclose all of the limitations of claim 7 (addressed above). Chen further discloses:
The interconnect bridge (140) can be bonded to dies (270a/270b) by hybrid/direct bonding (Fig. 3a-3f).
It would have been obvious to those having ordinary skill in the art at the time of invention to hybrid bond the interconnect bridge to the first and second die because it will establish shorter signal paths between the dies and the interconnect bridge thereby improving signal/power integrity (Paragraph [0053]).
Regarding claim 19, Li further discloses:
disposing the first semiconductor die, second semiconductor die, and interconnect bridge over a second substrate (103); and
A bond wire (109) from the second substrate to the first die.
Regarding claim 20, 22-24, Li disclose a semiconductor device comprising:
providing a first electrical component (101);
disposing a second electrical component (102) adjacent to the first electrical component;
forming an interconnect bridge (104) by, providing a silicon substrate including an integrated passive substrate (Paragraph [0074]),
and disposing the interconnect bridge over the first electrical component and second electrical component (Fig. 1).
Li does not explicitly disclose the interconnection bridge includes a conductive trace formed over a second surface of the second substrate and electrically coupled from the first semiconductor die to the second semiconductor die, a conductive via formed through the second substrate, and an integrated passive device (IPD) formed over a first surface of the second substrate and electrically coupled to the first semiconductor die or second semiconductor die through the conductive via. However Foo discloses a semiconductor device comprising:
An interconnect bridge (Fig. 1) including a conductive trace (130; Paragraph [0036) formed on a first surface of a bridge substrate (102) and electrically coupled dies (Fig. 2, 252/254) wherein an integrated passive device such as a capacitor formed by layers (116/118/114) is formed over a second surface of the substrate and electrically connected to the dies (252/254).
Second conductive traces (122/124) formed over the surface where the capacitor is formed.
It would have been obvious to those having ordinary skill in the art at the time of invention to form the interconnect bridge including a passive device and conductive traces on surfaces of a substrate because it will form a bridge capable of enabling shorter decoupling capacitance connection and improve power integrity of a multi-chip package (Paragraph [0014]).
Further Chen discloses a semiconductor device comprising:
A bridge die (Fig. 2d, 140) having one or more passive devices such as a capacitor (145) within a substrate (141-1) and having conductive via (143) formed through the substrate electrically coupling the passive device to first and second dies (170a/170c).
It would have been obvious to those having ordinary skill in the art at the time of invention to form conductive via through the substrate of the interconnect bridge because it will establish an electrical pathway between the dies and the passive as well as establish shorter electrical pathways for faster signal transmission between components of the package.
Regarding claim 21, Li, Foo, and Chen disclose all of the limitations of claim 7 (addressed above). Chen further discloses:
The interconnect bridge (140) can be bonded to dies (270a/270b) by hybrid/direct bonding (Fig. 3a-3f).
Regarding claim 25, Li further discloses:
disposing the first electrical component, second electrical component, and interconnect bridge over a second substrate (103); and
forming a bond wire (109) from the second substrate to the first electrical component.
Response to Arguments
Applicant's arguments filed April 27, 2026 have been fully considered but they are not persuasive. Applicant argument Li disclosure of the interconnect bridge being a passive silicon board and the same as a integrated passive device is agreed upon however Foo still discloses an interconnection bridge having passive device such as a capacitor (116/188/114) therefore the combination of Li and Foo meets the limitations of an interconnect bridge including an integrated passive device on a surface of a substrate of the interconnect bridge. Applicant argument that Foo discloses trench capacitors and does not disclose a conductive layer formed over the substrate patterned into a capacitor is not considered persuasive because the surface of the substrate that the trench capacitors of Foo are formed over is considered a second surface wherein the capacitor is formed by patterning a conductive layer (114) over a surface of the substrate different than the first surface the conductive trace is formed on. Further applicant argument of Chen disclosing a passive device and interconnect structure on same surface is not considered persuasive because while Chen discloses an interconnect bridge (140) having a passive device therein, Chen is not relied upon for a passive device and interconnect structure on opposite surface as Foo is relied upon to teach that limitation. Chen is instead relied upon for teaching a conductive via extend through a substrate of an interconnect bridge as disclosed above. Further Chen discloses die (140) may be used as bridge die (Paragraph [0041]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON C FOX whose telephone number is (571)270-5016. The examiner can normally be reached M-F 9:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRANDON C FOX/Examiner, Art Unit 2818
/DAVID VU/Primary Examiner, Art Unit 2818
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