Prosecution Insights
Last updated: October 02, 2026
Application No. 18/582,183

STATIC RANDOM-ACCESS MEMORY AND INTEGRATED CIRCUIT LAYOUT THEREOF

Non-Final OA §112
Filed
Feb 20, 2024
Priority
Mar 20, 2023 — CN 202310280177.0
Examiner
CHOI, WOO H
Art Unit
2827
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Shanghai Huali Microelectronics Corporation
OA Round
2 (Non-Final)
84%
Grant Probability
Favorable
2-3
OA Rounds
4m
Est. Remaining
79%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
76 granted / 91 resolved
+15.5% vs TC avg
Minimal -4% lift
Without
With
+-4.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
24 currently pending
Career history
113
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
20.9%
-19.1% vs TC avg
§102
14.0%
-26.0% vs TC avg
§112
29.7%
-10.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 91 resolved cases

Office Action

§112
DETAILED ACTION 1. Claims 1-9 are pending in this application filed on February 20, 2024 Notice of Pre-AIA or AIA Status 2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings 3. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the sleep control module, the memory cell array module, a word line drive power supply module comprising a power switch transistor, and power switch transistor connections to other elements must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 4. The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. 5. Claims 1-9 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The claim recites the limitation “sleep logic enable signal” that controls the power supply switch depending on the operating mode of the memory system. However, the “sleep logic enable signal” is merely a control signal that is either set to 1 or zero (see paragraph [0028]) that is presumably generated and used by other logic circuits or sleep control module to control the power switch, not a structure that is capable of controlling the operation of the power switch on its own as claimed. The specification does not describe a signal that is capable of controlling the operation of a power switch transistor based in the operating mode of the memory system in the manner claimed. 6. Claims 1-9 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. The claim recites the limitation “sleep logic enable signal” that controls the power supply switch based on the operating mode of the memory system. As discussed above. The “sleep logic enable signal” is merely a signal that can take on a value of 1 or 0. The specification does not enable one skilled in the art make and use the sleep logic enable signal that can the control the operation of the power switch based on an operating mode of the memory on its own as claimed. Conclusion 7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Woo H Choi whose telephone number is (571)272-4179. The examiner can normally be reached 9 am - 5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hetul Patel can be reached on (571) 272-4184. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Woo H Choi/ Primary Examiner, Art Unit 3992
Read full office action

Prosecution Timeline

Feb 20, 2024
Application Filed
May 14, 2026
Non-Final Rejection mailed — §112
Aug 13, 2026
Response Filed
Sep 30, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12744100
MEMORY DEVICE AND MEMORY TESTING
1y 11m to grant Granted Sep 22, 2026
Patent RE51034
AUDIO DEVICE AND COMPUTER READABLE PROGRAM
2y 4m to grant Granted Sep 15, 2026
Patent 12731625
MEMORY DEVICE RELATED TO A READ VOLTAGE AND AN OPERATION METHOD OF THE MEMORY DEVICE
2y 1m to grant Granted Sep 08, 2026
Patent 12718888
OPERATIONS ON PARTIALLY PROGRAMMED BLOCKS
2y 1m to grant Granted Aug 25, 2026
Patent 12706132
OPERATION METHOD OF SEMICONDUCTOR DEVICE
2y 1m to grant Granted Aug 11, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
84%
Grant Probability
79%
With Interview (-4.1%)
2y 11m (~4m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 91 resolved cases by this examiner. Grant probability derived from career allowance rate.

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