Prosecution Insights
Last updated: October 22, 2026
Application No. 18/582,200

PIXEL SENSOR ARRAYS AND METHODS OF FORMATION

Non-Final OA §102§103
Filed
Feb 20, 2024
Examiner
BOULGHASSOUL, YOUNES
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
470 granted / 532 resolved
+20.3% vs TC avg
Moderate +7% lift
Without
With
+6.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
27 currently pending
Career history
565
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
39.1%
-0.9% vs TC avg
§102
32.8%
-7.2% vs TC avg
§112
23.1%
-16.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 532 resolved cases

Office Action

§102 §103
Attorney’s Docket Number: P20232473US01 Filing Date: 02/20/2024 Claimed Foreign Priority Date: none Applicants: Lu et al. Examiner: Younes Boulghassoul DETAILED ACTION This Office action responds to the Election filed on 05/27/2026. Remarks The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election without traverse of Group Invention II (directed to a method of making a semiconductor structure), in the reply filed on 05/27/2026, is acknowledged. Applicant cancelled claims 1-14, added new claims 21-34, and indicated that claims 15-34 read on the elected Group Invention. The examiner agrees. Accordingly, pending in this application are claims 15-34. EXAMINER’S AMENDMENT On 06/23/2026, the examiner contacted Applicant’s representative to ask for clarifications about new claim 22, as the examiner could not map the claim’s limitations to an embodiment supported by the disclosure as originally filed. Applicant’s representative acknowledged the issue and indicated that the claim should have recited instead --forming a second grid extension, of the plurality of grid extensions, over a second portion of a second photodiode, of the plurality of photodiodes, from a second side of the second photodiode…--, as supported by Fig. 4C. An agreement was reached, and the correction to the claim has been incorporated in the instant examination on merit, as detailed below. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 15, 20, 22-23, 26, 29, 31, and 33 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (US2020/0099846). Regarding Claim 15, Cheng (see, e.g., Figs. 2-3 and 6; and Par. [0023]-[0038]) shows all aspects of the instant invention, including a method, comprising: - forming a plurality of photodiodes (e.g., photodiodes of pixels 120-128,160) in a semiconductor layer of a pixel sensor array (e.g., in semiconductor device substrate 110 of image sensor device 100) - forming a deep trench isolation (DTI) structure around the plurality of photodiodes in the semiconductor layer (e.g., DTI comprising isolation structures 180-184) - forming a metal grid structure (e.g., metal grid structure 270) above the semiconductor layer and above the DTI structure wherein forming the metal grid structure includes forming a plurality of grid extensions (e.g., portions 270B/C above each “small” pixel 160) that extend laterally outward from the metal grid structure and from the DTI structure wherein each of the plurality of grid extensions extends at least partially over a respective photodiode of the plurality of photodiodes (see, e.g., Par. [0026],[0037]: image sensor device 100 includes a plurality of “small” pixels 160, and each portions 270B/C extend over a respective 160 to define a smaller opening 290 vs. openings 280-282) Regarding Claim 20, Cheng (see, e.g., Fig. 6 and Par. [0043]-[0044]) shows forming a plurality of color filter regions (e.g., color filters 400-402,410) over the plurality of photodiodes, wherein a subset of the plurality of color filter regions are formed in between the metal grid structure and the plurality of grid extensions. Regarding Claim 22, Cheng (see, e.g., Figs. 2-3 and 6; and Par. [0023]-[0038]) discloses that, in a top view, “small” pixels 160 are overlapped by grid portions along all four edges of said “small” pixels (see, e.g., Fig. 3: portions 270B-C overlap 160 along a left-right direction, and other unlabeled portions 270u overlap 160 along a top-bottom direction). Therefore, Cheng shows that forming the plurality of grid extensions comprises: - forming a first grid extension, of the plurality of grid extensions, over a first portion of a first photodiode, of the plurality of photodiodes, from a first side of the first photodiode (e.g., over a first pixel 160 and covered by a left grid portion 270B) - forming a second grid extension, of the plurality of grid extensions, over a second portion of a second photodiode, of the plurality of photodiodes, from a second side of the second photodiode (e.g., over a second pixel 160 and covered by a top grid portion 270u), wherein the first side and the second side are approximately orthogonal (e.g., left-right direction vs. top-bottom direction). Regarding Claim 23, Cheng (see, e.g., Fig. 6 and Par. [0044]) discloses that the color filter above each “small” pixel 160 is a grey filer 410. Therefore, Cheng shows that forming the plurality of grid extensions comprises: - forming a first grid extension, of the plurality of grid extensions, over a first portion of a first photodiode of the plurality of photodiodes (e.g., over a first pixel 160 and covered by a grid portion 270B-C) - forming a second grid extension, of the plurality of grid extensions, over a second portion of a second photodiode of the plurality of photodiodes (e.g., over a second pixel 160 and covered by a grid portion 270B-C) - forming a first color filter over the first photodiode (e.g., a grey color filter 410) - forming a second color filter over the second photodiode (e.g., another grey color filter 410) - wherein the first color filter and the second color filter are configured to pass a same wavelength range for incident light (e.g., both 410 are grey color filters). Regarding Claim 26, Cheng (see, e.g., Par. [0026],[0037]) discloses that image sensor device 100 includes a plurality of “small” pixels 160, and each portions 270B/C extend over a respective 160 to define a smaller opening 290 vs. openings 280-282), wherein pixels 120-128,160 have substantially the same size. Therefore, Cheng (see, e.g., Figs. 2-3 and 6; and Par. [0023]-[0038]) shows that forming the plurality of grid extensions comprises: - forming a first grid extension, of the plurality of grid extensions, over a first portion of a first photodiode of the plurality of photodiodes (e.g., over a first pixel 160 and covered by a grid portion 270B-C) - forming a second grid extension, of the plurality of grid extensions, over a second portion of a second photodiode of the plurality of photodiodes (e.g., over a second pixel 160 and covered by a grid portion 270B-C) - wherein a cross-sectional width of the first photodiode and a cross-sectional width of the second photodiode are approximately equal (e.g., width 330). Regarding Claim 29, Cheng (see, e.g., Figs. 2-3 and 6; and Par. [0023]-[0038]) shows that forming the plurality of grid extensions comprises: - forming a first grid extension, of the plurality of grid extensions, over a first portion of a first photodiode of the plurality of photodiodes (e.g., over a first pixel 160 and covered by a grid portion 270B-C) - wherein a cross-sectional width of a top surface of the first grid extension is less than a cross-sectional width of a bottom surface of the first grid extension (see, profile of grid portion 270B-C). Regarding Claim 31, Cheng (see, e.g., Figs. 2-3 and 6; and Par. [0023]-[0038]) shows that a cross-sectional width of a top surface of the plurality of grid extensions is less than a cross-sectional width of a bottom surface of the plurality of grid extension (see, profile of grid portions 270B-C). Regarding Claim 33, Cheng (see, e.g., Figs. 2-3 and 6; and Par. [0023]-[0038]) shows all aspects of the instant invention, including a method, comprising: - forming a plurality of pixel sensors arranged in a grid (e.g., radiation-sensing pixel regions arranged in a 3x3 grid, and comprising pinned layer photodiodes 120-128,160 and transfer gate structures 131-135) - forming a metal grid structure (e.g., metal grid structure 270) above photodiodes of the plurality of pixel sensors (e.g., above pixel photodiodes 120-128,160) wherein the metal grid structure surrounds the photodiodes of the plurality of pixel sensors (see, e.g., Fig. 3) wherein the metal grid structure includes grid extensions that laterally extend from the metal grid structure (e.g., portions 270B/C above each “small” pixel 160) and over at least a portion of photodiodes of a subset of the plurality of pixel sensors (see, e.g., Par. [0026],[0037]: image sensor device 100 includes a plurality of “small” pixels 160, and each portions 270B/C extend over a respective 160 to define a smaller opening 290 vs. openings 280-282). Claims 15, 18-21, 24, 26, and 33-34 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miyatani et al. (US2022/0377275). Regarding Claim 15, Miyatani (see, e.g., Figs. 4-5 and Par. [0125]-[0146]) shows all aspects of the instant invention, including a method, comprising: - forming a plurality of photodiodes (e.g., photodiodes 121e) in a semiconductor layer of a pixel sensor array (e.g., in photoelectric conversion layer Z11 of pixel array unit of the imaging device 121) - forming a deep trench isolation (DTI) structure around the plurality of photodiodes in the semiconductor layer (e.g., deep isolating trenches comprising light shielding films 121g, formed at boundaries between respective pixels 121a to prevent electrical and optical crosstalk) - forming a metal grid structure (e.g., metal light shielding film 121b) above the semiconductor layer and above the DTI structure wherein forming the metal grid structure includes forming a plurality of grid extensions that extend laterally outward from the metal grid structure and from the DTI structure (see, e.g., Fig. 5: protrusions 121b over 121e) wherein each of the plurality of grid extensions extends at least partially over a respective photodiode of the plurality of photodiodes (see, e.g., Fig. 4: protrusions 121b over 121e) Regarding Claim 18, Miyatani (see, e.g., Figs. 4-5 and Par. [0125]-[0146]) shows that forming the plurality of grid extensions comprises: forming the plurality of grid extensions such that two or more of the plurality of grid extensions have different top view shapes (e.g., Par. [0128]: 121b-x can be rectangles having different widths). Regarding Claim 19, Miyatani (see, e.g., Figs. 4-5 and Par. [0125]-[0146]) shows that forming the plurality of grid extensions comprises: - forming a first grid extension (e.g., 121b-1), of the plurality of grid extensions, such that the first grid extension covers a first percentage of an area of a top surface of a first photodiode (e.g., 121e-1) of the plurality of photodiodes - forming a second grid extension (e.g., 121b-2), of the plurality of grid extensions, such that the second grid extension covers a second percentage of an area of a top surface of a second photodiode (e.g., 121e-2) of the plurality of photodiodes, wherein the first percentage is greater than the second percentage (e.g., Par. [0128]: 121b-x can be rectangles having different widths, thus one of the two grid extensions will have a coverage percentage bigger than the other grid extension). Regarding Claim 20, Miyatani (see, e.g., Figs. 4-5 and Par. [0133]-[0135]) shows: - forming a plurality of color filter regions (e.g., color filters 121d-1 and 121d-2) over the plurality of photodiodes wherein a subset of the plurality of color filter regions are formed in between the metal grid structure and the plurality of grid extensions (see, e.g., Fig. 5). Regarding Claim 21, Miyatani (see, e.g., Figs. 4-5 and Par. [0128]) shows that forming the plurality of grid extensions comprises: - forming a first grid extension (e.g., 121b-1), of the plurality of grid extensions, over a first portion of a first photodiode (e.g., 121e-1), of the plurality of photodiodes - forming a second grid extension (e.g., 121b-2), of the plurality of grid extensions, over a second portion of a second photodiode (e.g., 121e-2) of the plurality of photodiodes wherein the first portion is facing away from the second photodiode wherein the second portion is facing away from the first photodiode. Regarding Claim 24, Miyatani (see, e.g., Figs. 4-5 and Par. [0125]-[0146]) shows that forming the plurality of grid extensions comprises: - forming a first grid extension (e.g., 121b-1), of the plurality of grid extensions, over a first portion of a first photodiode (e.g., 121e-1) of the plurality of photodiodes wherein the first grid extension laterally extends a first extension distance over the first portion of the first photodiode - forming a second grid extension (e.g., 121b-2), of the plurality of grid extensions, over a second portion of a second photodiode (e.g., 121e-2) of the plurality of photodiodes wherein the second grid extension laterally extends a second extension distance over the second portion of the second photodiode wherein the first extension distance is different than the second extension distance (e.g., Par. [0128]: 121b-x can be rectangles having different widths). Regarding Claim 26, Miyatani (see, e.g., Figs. 4-5 and Par. [0125]-[0146]) shows that forming the plurality of grid extensions comprises: - forming a first grid extension (e.g., 121b-1), of the plurality of grid extensions, over a first portion of a first photodiode (e.g., 121e-1) of the plurality of photodiodes - forming a second grid extension (e.g., 121b-2), of the plurality of grid extensions, over a second portion of a second photodiode (e.g., 121e-2) of the plurality of photodiodes wherein a cross-sectional width of the first photodiode and a cross-sectional width of the second photodiode are approximately equal (see, e.g., Fig. 5) Regarding Claim 33, Miyatani (see, e.g., Figs. 4-5 and Par. [0125]-[0146]) shows all aspects of the instant invention, including a method, comprising: - forming a plurality of pixel sensors arranged in a grid (e.g., pixels 121a arranged in a 6x6 grid, each comprising photodiodes 121e and pixel transistors 162-166) - forming a metal grid structure (e.g., metal light shielding film 121g,121b) above photodiodes of the plurality of pixel sensors (e.g., above pixel photodiodes 121e) wherein the metal grid structure surrounds the photodiodes of the plurality of pixel sensors (e.g., 121g are formed at boundaries between pixels) wherein the metal grid structure includes grid extensions that laterally extend from the metal grid structure and over at least a portion of photodiodes of a subset of the plurality of pixel sensors (e.g., 121b are formed at the light receiving surface of pixels). Regarding Claim 34, Miyatani (see, e.g., Figs. 4-5 and Par. [0125]-[0146]) shows all aspects of the instant invention, including a method, comprising: - forming a plurality of pixel sensors arranged in a pixel sensor array (e.g., pixels 121a arranged in a 6x6 array, each comprising photodiodes 121e and pixel transistors 162-166) - forming a metal grid structure e.g., metal light shielding film 121g,121b) above photodiodes of the plurality of pixel sensors (e.g., above pixel photodiodes 121e) wherein the metal grid structure surrounds the photodiodes of the plurality of pixel sensors (e.g., 121g are formed at boundaries between pixels) wherein forming the metal grid structure includes: forming a first grid extension (e.g., 121b-1) that laterally extends from the metal grid structure over at least a portion of a first photodiode (e.g., 121e-1) of a first pixel sensor (e.g., 121a-1) of the plurality of pixel sensors forming a second grid extension (e.g., 121b-2) that laterally extends from the metal grid structure over at least a portion of a second photodiode (e.g., 121e-2) of a second pixel sensor (e.g., 121a-2) of the plurality of pixel sensors wherein a first extension distance, that the first grid extension laterally extends over the at least the portion of the first photodiode, is different than a second extension distance that the second grid extension laterally extends over the at least the portion of the second photodiode (see, e.g., Fig. 4 and Par. [0128]: the widths by which 121b-1 and 121b-2 shield the light receiving regions of their respective photodiodes from light can be different) Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US2020/0099846). Regarding Claim 25, Cheng (see, e.g., Figs. 2-3 and 6; and Par. [0023]-[0038]) shows that forming the plurality of grid extensions comprises: - forming a first grid extension, of the plurality of grid extensions, over a first portion of a first photodiode of the plurality of photodiodes (e.g., over a first pixel 160 and covered by a grid portion 270B-C) - forming a second grid extension, of the plurality of grid extensions, over a second portion of a second photodiode of the plurality of photodiodes (e.g., over a second pixel 160 and covered by a grid portion 270B-C) Furthermore, Cheng (see, e.g., Fig. 4 and Par. [0039]) teaches that the QE modulation of a pixel can further be achieved by additionally reducing the size of the pixel, such that a lateral dimension 340 of “small” pixel 160 that is substantially smaller than the lateral dimension 330 (e.g., at least 50% smaller) of other pixels. Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a cross-sectional width of the first photodiode being greater than a cross-sectional width of the second photodiode in the method of Cheng, because it is known in the semiconductor manufacturing art that the QE of a pixel can be further modulated by reducing the lateral dimension of the pixel as compared to the width of other pixels, as taught by Cheng himself, and applying a known method step for its conventional purpose would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007). Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US2020/0099846) in view of Kuo et al. (US2023/0378230). Regarding Claim 17, Cheng (see, e.g., Figs. 2-3 and 6; and Par. [0023]-[0038]) shows that forming the metal grid structure comprises: forming the metal grid structure (e.g., 270) such that a cross- sectional width of a top surface of a section of the metal grid structure is less than a cross- sectional width of a bottom surface of the section of the metal grid structure. However, Cheng is silent about the steps of forming the metal grid structure comprising depositing a layer of metal material above the semiconductor layer; and etching the layer of metal material to form the metal grid structure. Kuo (see, e.g., Figs. 10-12 and Par. [0057]-[0062]), on the other hand and in the same field of endeavor, teaches that steps of manufacturing a metal grid structure 108, comprise: depositing a layer of metal material 1004 above a semiconductor layer 104; and etching the layer of metal material, using mask 1102, to form the metal grid structure 108. Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have steps of forming the metal grid structure comprising depositing a layer of metal material above the semiconductor layer; and etching the layer of metal material to form the metal grid structure in the method of Cheng, because it is known in the semiconductor manufacturing art that metal grid structures can be formed by mask-assisted etching of an initial metal layer, as taught by Kuo, and applying known method steps for their conventional purpose would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007). Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Miyatani et al. (US2022/0377275) in view of Kuo et al. (US2023/0378230), and in view of Kim et al. (US2024/0258346). Regarding Claims 16 or 17, Miyatani is silent about the details of manufacturing steps for forming the metal grid structure, such as steps of depositing a layer of metal material above the semiconductor layer, and etching the layer of metal material to form the metal grid structure. Kuo (see, e.g., Figs. 10-12 and Par. [0057]-[0062]), on the other hand and in the same field of endeavor, teaches that steps of manufacturing a metal grid structure 108, comprise: depositing a layer of metal material 1004 above a semiconductor layer 104; and etching the layer of metal material, using mask 1102, to form the metal grid structure 108. Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have steps of forming the metal grid structure comprising depositing a layer of metal material above the semiconductor layer; and etching the layer of metal material to form the metal grid structure in the method of Miyatani, because it is known in the semiconductor manufacturing art that metal grid structures can be formed by mask-assisted etching of an initial metal layer, as taught by Kuo, and applying known method steps for their conventional purpose would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007). Furthermore, with regards to the particular shapes of the metal grid structure claimed, i.e., a cross-sectional width of a top surface of a section of the metal grid structure is greater than a cross-sectional width of a bottom surface of the section of the metal grid structure (as required by claim 16), and a cross-sectional width of a top surface of a section of the metal grid structure is less than a cross-sectional width of a bottom surface of the section of the metal grid structure (as required by claim 17), it is noted that the specification fails to provide teachings about the criticality of having the cross-sectional widths of the top and bottom surfaces arranged as claimed. Therefore, absent any criticality, these limitations are only considered to be an obvious modification of the top and bottom surfaces widths of the metal grid structure disclosed by Miyatani in view of Kuo, as the Court has held that a change in shape or configuration, without any criticality, is within the level of skill in the art, and the particular arrangements of cross-sectional widths of the top and bottom surfaces claimed by applicant are nothing more than one of numerous surfaces arrangements that a person having ordinary skill in the art will find obvious to provide using routine experimentation based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976). Additionally, the particular arrangements of cross-sectional widths of the top and bottom surfaces claimed are known in the art, as disclosed by Kim (see, e.g., Figs. 4-6), who discloses that a pixel fence patten 230 can be manufactured with top and bottom surfaces being substantially equal, having a wider top surface, or having a wider bottom surface. Accordingly, Miyatani in view of Kuo and in further view of Kim teaches that a cross-sectional width of a top surface of a section of the metal grid structure is greater than a cross-sectional width of a bottom surface of the section of the metal grid structure, as required by claim 16; or that a cross-sectional width of a top surface of a section of the metal grid structure is less than a cross-sectional width of a bottom surface of the section of the metal grid structure, as required by claim 17. Claims 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over Miyatani et al. (US2022/0377275) in view of Kageyama et al. (US2020/0314347). Regarding Claim 27, Miyatani (see, e.g., Figs. 4-5 and Par. [0125]-[0146]) shows that forming the plurality of grid extensions comprises: - forming a first grid extension (e.g., 121b-1), of the plurality of grid extensions, over a first portion of a first photodiode (e.g., 121e-1) of the plurality of photodiodes - forming a second grid extension (e.g., 121b-2), of the plurality of grid extensions, over a second portion of a second photodiode (e.g., 121e-2) of the plurality of photodiodes However, Miyatani discloses the grid extensions to be substantially rectangular in top view. Therefore, Miyatani is silent about the first grid extension and the second grid extension each have an approximately triangular top view shape. Kageyama (see, e.g., Figs. 16-35), on the other hand and in the same field of endeavor, teaches that phase difference detection pixels 131x are implemented with metal light shielding portions 133x formed above a pixel photodiode, therein the metal light shielding portions can be rectangular or triangular shaped in a top view. Accordingly, it would have been obvious to one of ordinary skill in the art to have the first grid extension and the second grid extension each have an approximately triangular top view shape in the method of Miyatani, because both shapes are known in the semiconductor art as equivalent and effective patterns for forming the metal light shielding portions of phase difference detection pixels, as suggested by Kageyama, and selecting among them would have been obvious to the skilled artisan. See In re KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007). Regarding Claim 28, Miyatani (see, e.g., Figs. 4-5 and Par. [0125]-[0146]) shows that forming the plurality of grid extensions comprises: - forming a first grid extension (e.g., 121b-1), of the plurality of grid extensions, over a first portion of a first photodiode (e.g., 121e-1) of the plurality of photodiodes wherein the first grid extension has an approximately rectangular top view shape - forming a second grid extension (e.g., 121b-2), of the plurality of grid extensions, over a second portion of a second photodiode (e.g., 121e-2) of the plurality of photodiodes However, Miyatani discloses the second grid extension to be substantially rectangular in top view. Therefore, Miyatani is silent about the second grid extension having an approximately triangular top view shape. Also, see comments stated above in Par. 45-46 with regards to Claim 27, which are considered repeated here, as applied to the shape of second grid extension. Claims 29-32 are rejected under 35 U.S.C. 103 as being unpatentable over Miyatani et al. (US2022/0377275) in view of Kim et al. (US2024/0258346). Regarding Claims 29 or 30, Miyatani (see, e.g., Figs. 4-5 and Par. [0125]-[0146]) shows that forming the plurality of grid extensions comprises: - forming a first grid extension (e.g., 121b-1), of the plurality of grid extensions, over a first portion of a first photodiode (e.g., 121e-1) of the plurality of photodiodes However, while Miyatani is silent about a cross-sectional width of a top surface of the first grid extension being less than a cross-sectional width of a bottom surface of the first grid extension (as required by claim 29); or a cross-sectional width of a top surface of the first grid extension being greater than a cross-sectional width of a bottom surface of the first grid extension (as required by claim 30), it is noted that the specification fails to provide teachings about the criticality of having the cross-sectional widths of the top and bottom surfaces arranged as claimed. Also, see comments stated above in Par. 41-42 with regards to Claims 16-17, which are considered repeated here, as applied to the method of Miyatani. Accordingly, Miyatani in view of Kim teaches that a cross-sectional width of a top surface of the first grid extension being less than a cross-sectional width of a bottom surface of the first grid extension, as required by claim 29; or that a cross-sectional width of a top surface of the first grid extension being greater than a cross-sectional width of a bottom surface of the first grid extension, as required by claim 30. Regarding Claims 31 or 32, while Miyatani is silent about a cross-sectional width of a top surface of the first grid extension being less than a cross-sectional width of a bottom surface of the first grid extension (as required by claim 31); or a cross-sectional width of a top surface of the first grid extension being greater than a cross-sectional width of a bottom surface of the first grid extension (as required by claim 32), it is noted that the specification fails to provide teachings about the criticality of having the cross-sectional widths of the top and bottom surfaces arranged as claimed. Also, see comments stated above in Par. 41-42 with regards to Claims 16-17, which are considered repeated here, as applied to the method of Miyatani. Accordingly, Miyatani in view of Kim teaches that a cross-sectional width of a top surface of the first grid extension being less than a cross-sectional width of a bottom surface of the first grid extension, as required by claim 31; or that a cross-sectional width of a top surface of the first grid extension being greater than a cross-sectional width of a bottom surface of the first grid extension, as required by claim 32. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional reference cited disclose methods of manufacturing pixel arrays having metal grid structures comprising grid extensions, and having process steps similar to the instant inventions. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul at (571) 270-5514. The examiner can normally be reached on Monday-Friday 9am-6pm EST (Eastern Standard Time), or by e-mail via younes.boulghassoul@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814
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Prosecution Timeline

Feb 20, 2024
Application Filed
Jul 30, 2024
Response after Non-Final Action
Jun 23, 2026
Examiner Interview (Telephonic)
Oct 05, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
95%
With Interview (+6.9%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 532 resolved cases by this examiner. Grant probability derived from career allowance rate.

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