Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6, 7, 15-19 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Bu et al. (US Pat. Pub. 2006/0030128).
Regarding claim 1, Bu teaches an integrated chip, comprising:
an interconnect dielectric layer over a substrate [fig. 3c, 354];
an interconnect via within the interconnect dielectric layer [fig. 3c, 370 within a lower portion of 354, see annotated figure below];
an interconnect wire over the interconnect via and within the interconnect dielectric layer [fig. 3c, 370 within an upper portion of 354, see annotated figure below];
a protective layer surrounding the interconnect via, the interconnect via vertically extending through the protective layer to below a bottom of the protective layer [fig. 3c, 372, via portion of 370 extend through the protective layer to contact 44; and
wherein the protective layer continuously extends from along an outer sidewall of the interconnect via to along an outer sidewall of the interconnect wire in a first cross-sectional view [fig. 3c, 372 extends along an outer sidewall of the via to the outer sidewall of the wire].
PNG
media_image1.png
732
758
media_image1.png
Greyscale
Regarding claim 6, Bu discloses the integrated chip of claim 1, further comprising:
an etch stop layer disposed vertically below the interconnect dielectric layer and the protective layer and laterally around the interconnect via, wherein the protective layer has a sidewall that continuously extends from a top of the etch stop layer to a top of the interconnect dielectric layer in the first cross-sectional view [fig. 3c, 350 is below at least a portion of protective layer 372 and 372 has a sidewall that extends from the bottom of the interconnect dielectric layer 354 to a top including a portion that continuously extends from the top of the etch stop layer 350 to the top].
Regarding claim 7, Bu teaches the integrated chip of claim 1, wherein the interconnect via and the interconnect wire comprise a conducive core and a diffusion barrier laterally surrounding the conductive core [fig. 3c, conductive core 370, diffusion barrier 368].
Regarding claim 15, Bu discloses an integrated chip, comprising:
an inter-level dielectric arranged over a substrate [fig. 2c, 254[;
an interconnect structure disposed within the inter-level dielectric [fig. 2c, 268 and 70];
a dimensional control layer arranged laterally between a lower part of the interconnect structure and the inter-level dielectric [fig. 2c, 272a and 272b]; and
wherein the interconnect structure comprises a vertically extending surface that laterally contacts the inter-level dielectric over a first top surface of the dimensional control layer, as viewed in a first cross-sectional view [fig. 2c, 268 extends upward from where it touches the top surface of 254 above a surface of 272b].
Regarding claim 16, Bu teaches the integrated chip of claim 15 ,wherein the interconnect structure laterally and vertically contact the dimensional control layer [fig. 2c, 268 is above and extends across the top surface laterally of layer 272b].
Regarding claim 17, Bu discloses the integrated chip of claim 15, wherein the interconnect structure includes a diffusion barrier and a conductive material over the diffusion barrier [fig. 2c, diffusion barrier 268, conducive material 70].
Regarding claim 18, Bu teaches the integrated chip of claim 15, wherein the interconnect structure is directly over the first top surface of the dimensional control layer, as viewed along the first cross sectional view [fig. 2c, 268 is directly over a top surface of 272b].
Regarding claim 19, Bu discloses the integrated chip of claim 18, wherein the dimensional control layer has a second top surface as viewed along a second cross-sectional view, the second top surface being over the first top surface [fig. 2c, 272a has a second top surface being over the first top surface, only one cross sectional view is provided but 272 extends around 268/70 and would have the second top surface above the first as it extends].
Claim(s) 1-3, 6,7, 15-19 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Hong et al. (US Pat. Pub. 2019/0221475).
Regarding claim 1, Hong teaches an integrated chip, comprising:
an interconnect dielectric layer over a substrate [fig. 20, 15];
an interconnect via within the interconnect dielectric layer [fig. 20, Va (25v, 23v)];
an interconnect wire over the interconnect via and within the interconnect dielectric layer [fig. 20, Wa (25a, 23a)];
a protective layer surrounding the interconnect via, the interconnect via vertically extending through the protective layer to below a bottom of the protective layer [fig. 20, 21w1, 21v1, 21w2, 21v2, Va extends through the protective layer]; and
wherein the protective layer continuously extends from along an outer sidewall of the interconnect via to along an outer sidewall of the interconnect wire in a first cross-sectional view [fig. 1, 21w1, 21v1, 21w2, 21v2, 21w1 and 21v1 extends continuously along an outer sidewall of the interconnect via to an outer sidewall of the interconnect wire].
Regarding claim 2, Hong discloses the integrated chip of claim 1, further comprising:
A second interconnect wire laterally separated from the interconnect wire by the interconnect dielectric layer, wherein the protective layer lines sidewalls and lower surface of the second interconnect wire as viewed in the first cross-sectional view [fig. 20, second wire Wb, protective layer 21wb extends along sidewalls and the lower surface of Wb].
Regarding claim 3, Hong teaches the integrated chip of claim 1, further comprising: a second interconnect wire disposed within the interconnect dielectric layer, wherein the protective layer laterally and vertically separates the second interconnect wire from the interconnect dielectric layer as viewed in the first cross-sectional view [fig. 20, second wire Wb, protective layer 21wb separates Wb from 15].
Regarding claim 6, Hong discloses the integrated chip of claim 1, further comprising:
an etch stop layer disposed vertically below the interconnect dielectric layer and the protective layer and laterally around the interconnect via, wherein the protective layer has a sidewall that continuously extends from a top of the etch stop layer to a top of the interconnect dielectric layer in the first cross-sectional view [fig. 20 etch stop 13, 21v2 and 21w2 has a sidewall that extends from the top of 13 to a top of 15].
Regarding claim 7, Hong teaches the integrated chip of claim 1, wherein the interconnect via and the interconnect wire comprise a conducive core and a diffusion barrier laterally surrounding the conductive core [fig. 20, conductive core 25a/v and diffusion barrier 23a/v].
Regarding claim 15, Hong discloses an integrated chip, comprising:
an inter-level dielectric arranged over a substrate [fig. 1, 15];
an interconnect structure disposed within the inter-level dielectric [fig. 1, Va (25v, 23v) and Wa (25a, 23a)];
a dimensional control layer arranged laterally between a lower part of the interconnect structure and the inter-level dielectric [fig. 1, 21v1, 21w1, 21v2, 21w2]; and
wherein the interconnect structure comprises a vertically extending surface that laterally contacts the inter-level dielectric over a first top surface of the dimensional control layer, as viewed in a first cross-sectional view [fig. 1, Wa extends upward from a surface that touches 15 and extends over a top surface of 21v1].
Regarding claim 16, Hong teaches the integrated chip of claim 15 ,wherein the interconnect structure laterally and vertically contact the dimensional control layer [fig. 1, Wa laterally and vertically contacts 21w1 and 21v1].
Regarding claim 17, Hong discloses the integrated chip of claim 15, wherein the interconnect structure includes a diffusion barrier and a conductive material over the diffusion barrier [fig. 1, diffusion barrier 23a/v, conducive material 25a/v].
Regarding claim 18, Hong teaches the integrated chip of claim 15, wherein the interconnect structure is directly over the first top surface of the dimensional control layer, as viewed along the first cross sectional view [fig. 1, Wa directly over a top surface of 21v1].
Regarding claim 19, Hong discloses the integrated chip of claim 18, wherein the dimensional control layer has a second top surface as viewed along a second cross-sectional view, the second top surface being over the first top surface [fig. 1, 21w1 has a second top surface being over the first top surface of 21v1, only one cross sectional view is provided but 21w1 extends around Wa and Va and would have the second top surface above the first as it extends].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong as applied to claims 1-3,6,7, 15-19 above, and further in view of Ho et al. (US Pat. Pub. 2017/0288031).
Regarding claim 5, Hong fails to teach the protective layer comprises a metal oxide and instead teaches aluminum nitride. However, Ho teaches interconnect structures with a barrier/protective layer that can be formed from a variety of materials including aluminum nitride as well as aluminum oxide [paragraph [0046]].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Ho into the method of Hong by forming the protective layer out of aluminum oxide (metal oxide). The ordinary artisan would have been motivated to modify Hong in the manner set forth above for at least the purpose of utilizing known materials to ensure conductive material is blocked sufficiently [Ho, paragraph [0046]]. Additionally, art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP 2144.07.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong as applied to claims 1-3,6,7, 15-19 above, and further in view of Cheng et al. (US Pat. Pub. 2018/0061762).
Regarding 8, Hong fails to teach a width of the interconnect via being between 5nm and 300nm. However, Cheng teaches an interconnect structure with via openings, the openings being anywhere between 10nm and 80nm [paragraph [0026]].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Cheng into the method of Hong by forming the interconnect via with a width between 10nm and 80nm. The ordinary artisan would have been motivated to modify Hong in the manner set forth above for at least the purpose of reducing size while reducing contact resistance and improving performance [Cheng, paragraph [0014]].
Allowable Subject Matter
Claims 9-14 are allowed.
Claims 4 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 9, the prior art fails to disclose or suggest the device as claimed. Specifically, the prior art fails to teach the interconnect structure is directly over the dielectric layer and a part of the inter-level dielectric, the part of the inter-level dielectric having a larger heigh than the dielectric layer in a first cross-sectional view.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M PARKER whose telephone number is (571)272-8794. The examiner can normally be reached M-F 7:30am - 3:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOHN M PARKER/Primary Examiner, Art Unit 2899
Prosecution Insights