Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Species D (patterned thermal control layers and high thermal conductivity layers Fig. 6A) in the reply filed on 6/1/2026 is acknowledged.
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5, 7 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shaikh et al. (US Pub. No. 2020/0294884 A1), hereafter referred to as Shaikh.
As to claim 1, Shaikh discloses an integrated device (fig 1D, 150), comprising:
a substrate (fig 1D, IC die 114) comprising at least one active component ([0023]);
an interconnect structure (BGA on die 114 to substrate 103; [0070]) disposed on the substrate (114);
a bonding layer (108) disposed over the interconnect structure (BGA);
a carrier substrate (111) disposed over the interconnect structure (BGA);
a heat dissipating module (120) disposed over the carrier substrate (111); and
a first thermal control layer (102) disposed between the carrier substrate (111) and the heat dissipating module (120), the bonding layer and the interconnect structure, or the carrier substrate and the bonding layer, the first thermal control layer (102) comprising a phase change material ([0048]).
As to claim 2, Shaikh discloses the integrated device of claim 1 (paragraphs above),
a high thermal conductivity layer (117; [0068]) on a first side of the first thermal control layer (102).
As to claim 5, Shaikh discloses the integrated device of claim 1 (paragraphs above),
wherein the first thermal control layer comprises a solid-solid PCM ([0056]).
As to claim 7, Shaikh discloses an integrated device (fig 1D), comprising:
a substrate (114);
an active component ([0023]) on the substrate (114);
an interconnect structure (BGA) coupled to the active component (114);
a heat dissipating module (120) disposed over the interconnect structure (BGA); and
a first thermal control layer (102) disposed between the interconnect structure (BGA) and the heat dissipating module (120), wherein the first thermal control layer comprises a phase change material ([0048]).
As to claim 8, Shaikh discloses the integrated device of claim 7 (paragraphs above),
wherein the first thermal control layer comprises a solid-solid phase change material ([0056]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shaikh in view of Hite et al. (“NiTiHf shape memory alloys as phase change thermal storage materials” Acta Materialia, Vol. 218, 1 October 2021, 117175, provided on IDS received 2/22/2024), hereafter referred to as Hite.
As to claim 6, Shaikh discloses the integrated device of claim 5 (paragraphs above),
Shaikh does not explicitly disclose wherein the solid/solid-PCM comprises a shape memory alloy.
Nonetheless, Hite discloses wherein a SS-PCM comprises a shape memory alloy (abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to use the SS-PCM of Hite as the SS-PCM of Shaikh since this provides a very high figure of merit of the PCM.
Claim(s) 1, 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US Pub. No. 2023/0260867 A1), hereafter referred to as Huang, in view of Hsieh et al. (US Pub. No. 2013/0273694 A1), hereafter referred to as Hsieh, and further in view of Shaikh.
As to claim 1, Huang discloses an integrated device (fig 2, 200a), comprising:
a substrate (fig 2, 110) comprising at least one active component ([0018]);
an interconnect structure (108) disposed on the substrate (110);
a bonding layer (106) disposed over the interconnect structure (108);
a carrier substrate (102) disposed over the interconnect structure (108); and
a first thermal control layer (104) disposed between the carrier substrate (102) and the bonding layer (106).
Huang does not disclose a heat dissipating module disposed over the carrier substrate; and the first thermal control layer comprising a phase change material.
Nonetheless, Hsieh discloses a heat dissipating module (fig 8, 82) disposed over a carrier substrate (54) that is disposed over a substrate comprising an active component (40; [0009]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include a heat dissipating module over the carrier substrate of Huang as taught by Hsieh since this will improve thermal dissipation of the semiconductor device.
Additionally, Shaikh discloses wherein a thermal control layer comprises a phase change material ([0048]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the thermal control layer comprising the phase change material of Shaikh in the package of Huang in view of Hsieh since this will improve thermal management of the package by preventing overheating during a burst mode.
As to claim 3, Huang in view of Hsieh and Shaikh disclose the integrated device of claim 1 (paragraphs above).
Huang in view of Hsieh do not disclose the second thermal control layer.
Nonetheless, Shaikh discloses a phase change thermal control layer ([0048]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form a second thermal control layer disposed between a different one of the carrier substrate and the heat dissipating module, the bonding layer and the interconnect structure, or the carrier substrate and the bonding layer than the first thermal control layer as Shaikh teaches this will improve thermal management of the package by preventing overheating during a burst mode.
As to claim 4, Huang in view of Hsieh and Shaikh disclose the integrated device of claim 3 (paragraphs above).
Huang in view of Hsieh do not disclose the second thermal control layer.
Nonetheless, Shaikh discloses a phase change thermal control layer ([0048]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form a third thermal control layer disposed between a different one of the carrier substrate and the heat dissipating module, the bonding layer and the interconnect structure, or the carrier substrate and the bonding layer than the first thermal control layer and the second thermal control layer as Shaikh teaches this will improve thermal management of the package by preventing overheating during a burst mode.
Claim(s) 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Hsieh.
As to claim 14, Huang discloses a method of forming an integrated device ([0007]), comprising:
providing a substrate (fig 5, 110);
forming an active component on the substrate ([0038]);
forming an interconnect structure (108) on the substrate (110);
bonding a carrier substrate (fig. 8, 102) over the interconnect structure (108);
forming a thermal interface material (104) over the carrier substrate (102); and
after forming the interconnect structure (108) and before positioning the heat dissipating module (82 of Huang as combined below), forming a first thermal control layer (106) on the interconnect structure (108) or the carrier substrate (102).
Huang does not disclose positioning a heat dissipating module over the carrier substrate, wherein the thermal interface material thermally couples the carrier substrate to the heat dissipating module.
Nonetheless, Hsieh discloses positioning a heat dissipating module (fig 8, 82) over a carrier substrate (54), wherein a thermal interface material (84) thermally couples the carrier substrate (54) to the heat dissipating module (82).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to position the heat dissipating module of Hsieh over the carrier substrate of Huang as taught by Hsieh since this will improve heat dispersion of the semiconductor package.
As to claim 15, Huang in view of Hsieh disclose the method of claim 14 (paragraphs above).
Huang further discloses wherein forming the first thermal control layer further comprises:
forming the first thermal control layer (fig 7, 104) on the carrier substrate (102) before the carrier substrate is disposed on the interconnect structure (108); and
forming a bonding layer (106) on the interconnect structure (108), wherein after the carrier substrate (102) is disposed over the interconnect structure (108), the carrier substrate and the first thermal control layer (104) are mechanically coupled to the substrate by the bonding layer (106).
Allowable Subject Matter
Claims 9-13, and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or suggest wherein the first thermal control layer comprises a first side and a first plurality of protrusions extending from the first side, as recited in claim 9; or forming a second thermal control layer on the carrier substrate before the carrier substrate is disposed on the interconnect structure, wherein the second thermal control layer is spaced from the first thermal control layer by the carrier substrate; and bonding one of the first thermal control layer or the second thermal control layer to the bonding layer, as recited in claim 16; or depositing a material of the first thermal control layer within the plurality of grooves, such that the first thermal control layer has a first plurality of protrusions extending into the carrier substrate, as recited in claim 17; or forming a bonding layer on the interconnect structure; and when the first thermal control layer is to be between the carrier substrate and the bonding layer, forming a first high thermal conductivity layer after forming the first thermal control layer, such that the first high thermal conductivity layer is between the first thermal control layer and the bonding layer, as recited in claim 18; or depositing a material of the first thermal control layer onto the carrier substrate or the interconnect structure, wherein after the depositing of the material of the first thermal control layer, the first thermal control layer has a plurality of protrusions extending towards the carrier substrate and the interconnect structure, as recited in claim 19, or wherein when the first thermal control layer is to be formed on the interconnect structure, forming a first high thermal conductivity layer before forming the first thermal control layer, such that the first high thermal conductivity layer is between the first thermal control layer and the interconnect structure, as recited in claim 20. Claims 10-13 are allowable because of their dependence from claim 9.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 9,754,856B2; and US Pub. No. 2024/0014095A1, figure 15 with thermal module 506.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 6/24/2026
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