Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/582,902 filed on 02/21/2024.
Election/Restrictions
Applicant’s election without traverse of Invention I (claims 1-17) in the reply filed on 06/08/2026 is acknowledged.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 8-12 and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pub # 2024/0049393 to Yang et al. (Yang).
Regarding independent claim 1, Yang discloses an electronic module (Fig. 4), comprising:
a main printed circuit board (PCB) (namely system board 460, which is described as a system printed circuit board (¶0063) having a first surface;
a first chip substrate (PCB 402 is considered the claimed first chip substrate) disposed on the first surface of the main PCB (¶0063);
a second chip substrate (PCB 406 is considered the claimed first chip substrate) disposed on the first surface of the main PCB (¶0063); and
an intermediate PCB (PCB 404, which is considered the claimed intermediate PCB) supported by the main PCB (460), wherein at least a portion of the intermediate PCB (404) is disposed between the first chip substrate (402) and the second chip substrate (406), and wherein the intermediate PCB (404) electrically connects the first chip substrate (402) to the second chip substrate (406) (see ¶0067).
Regarding claim 2, Yang discloses wherein the intermediate PCB (Fig. 4: 404) comprises:
first pins (see Examiner’s Mark-up below and ¶0066; the intermediate PCB 404 comprises 402a-402c and each of 402a-402c comprises pins; see also Fig. 2c for pins) extending substantially parallel to the first surface of the main PCB (460) from the intermediate PCB (404) toward the first chip substrate (402); and
second pins (see Examiner’s Mark-up below and ¶0066; the intermediate PCB 404 comprises 402a-402c and each of 402a-402c comprises pins; see also Fig. 2c for pins) extending substantially parallel to the first surface of the main PCB (460) from the intermediate PCB (404) toward the second chip substrate (406),
wherein the first pins (see Examiner’s Mark-up below) and the second pins (see Examiner’s Mark-up below) are configured to electrically connect to the first chip substrate (402) and the second chip substrate (406), respectively.
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Regarding claim 3, Yang discloses wherein: the first chip substrate (402) comprises first contacts (402a-402c) oriented toward the intermediate PCB, wherein each first contact (402a-402c) is configured to electrically connect to a corresponding first pin of the first pins (see Examiner’s Mark-up above from claim 2); and the second chip substrate (406) comprises second contacts (402a-402c) oriented toward the intermediate PCB (460), wherein each second contact (402a-402c) is configured to electrically connect to a corresponding second pin of the second pins(see Examiner’s Mark-up below).
Regarding claim 4, Yang discloses wherein: the first contacts (402a-402c) are disposed on a first chip surface of the first chip substrate (402) that is substantially perpendicular to the first surface of the main PCB (460); and
the second contacts (402a-402c) are disposed on a second chip surface of the second chip substrate (406) that is substantially perpendicular to the first surface of the main PCB (460).
Regarding claim 5, Yang discloses wherein the first chip substrate (402) defines a first socket (see Examiner’s Mark-up below), the first socket comprising the first contacts (see Examiner’s Mark-up below), and wherein the second chip substrate (406) defines a second socket (see Examiner’s Mark-up below), the second socket comprising the second contacts (see Examiner’s Mark-up below).
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Regarding claim 8, Yang disclose wherein the intermediate PCB (404) comprises: a first portion (see Examiner’s Mark-up below) disposed between a first side of the first chip substrate and a first side of the second chip substrate; and a second portion extending along a second side of one of the first chip substrate or the second chip substrate.
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Regarding claim 9, Yang discloses the electronic module of claim 8 as previously discussed. As shown in Figure 4 (and the Examiner’s Mark up above from claim 8), the intermediate PCB 404 includes a first portion and a second portion. Under the broadest reasonable interpretation, the claimed “first portion” and “second portion” encompass respective regions of the intermediate PCB.
Specifically, the upper region of intermediate PCB 404 constitutes the claimed first portion and is electrically connected to the first side of the first chip substrate 402 through the conductive members (capacitor leads) 450a and 450b; and
the lower region of intermediate PCB 406 constitutes the claimed second portion and is electrically connected to the second side of the second chip substrate 406 through the conductive members 450a and 450b. Therefore, Yang teaches:
Regarding claim 10, Yang disclose wherein the intermediate PCB (404) comprises a third portion (see Examiner’s Mark-up below) extending along a third side (see Examiner’s Mark-up below) of the one of the first chip substrate (402) or the second chip substrate (406).
It is noted that because PCB 404 extends laterally beneath and beyond the chip substrate, a side region of PCB 404 may reasonably be considered the claimed third portion.
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Regarding claim 11, Yang discloses the electronic module of claim 10 as previously discussed. As shown in Figure 4 (and the Examiner’s Mark-up above from claim 10), the intermediate PCB 404 comprises a first portion and a third portion, which under the broadest reasonable interpretation correspond to respective regions of the intermediate PCB.
The first portion of intermediate PCB 404 is electrically connected to the first chip substrate 402 through conductive members 450a and 450b and the associated conductive PCB pads 402a, 402b, and 402c, thereby satisfying the limitation that the first portion is electrically connected to one of the first chip substrate or the second chip substrate.
Furthermore, the third portion of intermediate PCB 404 extends along a third side of second chip substrate 406 and is likewise electrically connected to that side of the chip substrate through conductive members 450a and 450b, thereby teaching the limitation that the third portion is electrically connected to the third side of the one of the first chip substrate or the second chip substrate.
Regarding claim 12, Yang discloses an intermediate PCB 404. As shown in Figure 4 and described in paragraphs 65–67, conductive members 450a and 450b provide electrical and mechanical connections between the stacked PCBs and between the electronic module and the system board 460. Under the broadest reasonable interpretation, the conductive members 450a and 450b, together with the corresponding attachment locations on intermediate PCB 404, constitute the claimed first and second attachment features configured to secure the intermediate PCB to the main PCB 460.
It is noted that claim 12 does not require the attachment feature to be formed integrally with the intermediate PCB. Claim 12 only recites:
“the intermediate PCB comprises a first attachment feature…”
Under BRI, a feature associated with or incorporated into the intermediate PCB assembly (such as the conductive members retained by PCB 404) can reasonably satisfy that language unless the specification clearly requires a narrower construction.
Regarding claim 15, Yang discloses the first chip substrate 402 and second chip substrate 406 (Fig. 4). As shown in Figure 4, first chip substrate 402 includes electronic components 408. Furthermore, ¶0067 teaches that second PCB 404 and third PCB 406 may also include one or more electronic components. Under the broadest reasonable interpretation, the recited first and second processing units encompass these electronic components. Therefore, Yang teaches a first processing unit on first chip substrate 402 and a second processing unit on second chip substrate 406, as recited.
Regarding claim 16, Yang discloses the electronic module of claim 15 in an assembled and operable configuration (Fig. 4). As described in ¶0065-0067, conductive members 450a and 450b, together with the conductive structures of intermediate PCB 404, provide electrical connections between the stacked PCBs. Accordingly, first processing unit 408 on first chip substrate 402 and the electronic component(s) on second chip substrate 406 are configured to communicate with each other via the electrical connection provided by intermediate PCB 404, as claimed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2024/0049393 to Yang et al. (Yang).
Regarding claim 17, Yang discloses the electronic module of claim 16, including a first chip substrate 402, a second chip substrate 406, an intermediate PCB 404, and conductive members 450a and 450b that electrically interconnect the stacked substrates (Fig. 4; see also corresponding paragraphs describing the stacked PCB interconnections). As discussed with respect to claim 16, the first processing unit (electronic component(s) 408 on first chip substrate 402) and the second processing unit (electronic component(s) on second chip substrate 406) communicate through electrical connections provided by intermediate PCB 404.
Yang does not explicitly disclose that the first processing unit and the second processing unit communicate with each other only via the electrical connection provided by the intermediate PCB, the first chip substrate, and the second chip substrate.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to configure the communication path between the first and second processing units to occur exclusively through the disclosed stacked electrical interconnection (i.e., through first chip substrate 402, intermediate PCB 404, second chip substrate 406, and conductive members 450a and 450b), because doing so would provide a single defined communication path, simplify routing of electrical signals, reduce unnecessary interconnection complexity, improve signal integrity, and facilitate reliable communication between the stacked processing units. Limiting communication to the existing electrical path merely represents the predictable use of the known interconnection architecture already disclosed by Yang to obtain its expected advantages.
Accordingly, it would have been obvious to modify Yang so that, in an operable configuration, the first processing unit and the second processing unit communicate only via the electrical connection provided by the intermediate PCB, the first chip substrate, and the second chip substrate, as recited.
Allowable Subject Matter
Claims 6-7 and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 6 recites:
“wherein the first surface of the main PCB defines a first processor socket and a second processor socket; wherein the first chip substrate comprises a first processor socket interface configured to electrically connect to the first processor socket, and wherein the first contacts and the first processor socket interface are on different surfaces of the first chip substrate; and wherein the second chip substrate comprises a second processor socket interface configured to electrically connect to the second processor socket, and wherein the second contacts and the second processor socket interface are on different surfaces of the second chip substrate.”
Claim 7 recites:
“wherein the intermediate PCB comprises: first test points configured to allow testing of first electrical connections between the first pins and the intermediate PCB, wherein each first test point corresponds to a first pin of the first pins; and second test points configured to allow testing of second electrical connections between the second pins and the intermediate PCB, wherein each second test point corresponds to a second pin of the second pins.”
Claim 13 recites:
“wherein: the first attachment feature comprises a first opening extending through the intermediate PCB, wherein the main PCB defines a first corresponding opening extending from the first surface to a second surface of the main PCB; and the second attachment feature comprises a second opening extending through the intermediate PCB, wherein the main PCB defines a second corresponding opening extending from the first surface to a second surface of the main PCB, wherein the first attachment feature and the first corresponding opening of the main PCB are configured to receive a first attachment member therethrough, and wherein the second attachment feature and the second corresponding opening of the main PCB are configured to receive a second attachment member therethrough.”
Each of the above recitations, interpreted in combination with all other limitations of the claim and all limitations of any claims they depend from, is not taught or rendered obvious by the prior art of record and are indicated as allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pat # 7,742,314 to Urashima et al., US Pub # 2009/0215231 to Inoue., US Pub # 2008/0192452 to Randall et al., US Pub # 2008/0055873 to Mi et al., US Pub # 2007/0121273 to Yamamoto et al. and US Pub # 2004/0257749 to Otsukaa et al.
Urashima discloses an electronic module (Figs. 1 and 23), a wiring board 10 or 110 comprised of a substantially rectangular plate-shaped board core 11 which is a wiring board for mounting on an IC chip and is formed of glass epoxy; a first buildup layer 31 (wiring laminated portion) formed on an upper surface 12 (core main surface) of the board core 11; and a second buildup layer 32 formed on a lower surface 13 (core reverse surface) of the board core 11, through hole conductors 16 are formed at a plurality of portions in the board core 11, the through hole conductors 16 connect and conduct the upper surface 12 side and the lower surface 13 side of the board core 11, the interior of each through hole conductor 16 is filled with a closure body 17 such as an epoxy resin, and conductor layers 41 formed of copper are respectively pattern-formed on the upper surface 12 and the lower surface 13 of the board core 11, and each conductor layer 41 is electrically connected to the through hole conductor 16.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHSEN AHMADI whose telephone number is (571)272-5062. The examiner can normally be reached M-F: 9:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William F Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHSEN AHMADI/Primary Examiner, Art Unit 2896
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