DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicants’ amendments filed 7/13/2026 have been entered and considered. The cancellation of claims 16-20 and the addition of claims 21-25 are acknowledged.
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-15 and 21-25 in the reply filed on 7/13/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 and 21-25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Huang et al. US 20220246479 A1 (hereinafter referred to as Huang).
Regarding claim 1, Huang teaches
A method (method of forming “nano-FETs”, para. 0011 FIG. 2-3C), comprising:
patterning a substrate (“substrate 50” para. 0011 FIG. 3) to form a fin (“fin 66” para. 0011) protruding from the substrate, wherein the fin has a first portion (protrusion of “substrate 50”), a second portion over the first portion (“first nanostructure 52A” para. 0021 FIG. 3), and a third portion over the second portion (“second nanostructure 54A” para. 0021);
forming shallow trench isolation (STI) regions (“shallow trench isolation (STI) regions 68” para. 0024 FIG. 4) over the substrate and surrounding the first portion of the fin;
forming a hard mask structure (“first spacer layer 80” and “second spacer layer 82” para. 0034 FIG. 7A) over the STI regions and surrounding the second portion of the fin, wherein the hard mask structure includes a first dielectric material (“second spacer layer 82” may comprise silicon nitride, para. 0034) different from a dielectric material of the STI region (“STI regions 68” comprise silicon oxide, para. 0024); and
forming a gate structure on the hard mask structure and across the fin (“gate dielectric layer 100” and “gate electrode 102” are formed on “first spacer 81”, which is a remaining portion of “first spacer layer 80”, para. 0074 FIG. 29A-29B).
Regarding claim 2, Huang teaches the method of claim 1, wherein forming the hard mask structure comprises: forming a first hard mask layer (“first spacer layer 80” para. 0034 FIG. 7A) of a second dielectric material (silicon oxide, para. 0034) over the fin; and
forming a second hard mask layer (“second spacer layer 82” para. 0034) of the first dielectric material (silicon nitride, para. 0034) over the first hard mask layer, wherein the second dielectric material is different from the first dielectric material (silicon oxide is different from silicon nitride).
Regarding claim 3, Huang teaches the method of claim 2, wherein the second dielectric material comprises silicon oxide (“first spacer layer 80” comprises silicon oxide), and the first dielectric material comprises silicon nitride (“second spacer layer 82” comprises silicon nitride).
Regarding claim 4, Huang teaches the method of claim 2, wherein the first hard mask layer has a U-shape when viewed from a cross-sectional view (“first spacer layer 80” and “second spacer layer 82” form a U-shape between adjacent “fins 66” as seen in FIG. 7A).
Regarding claim 21, Huang teaches
A method (“method of forming “nano-FETs”, para. 0011 FIG. 2-3C), comprising:
forming a fin (“fin 66” para. 0011) protruding from a substrate (“substrate 50” para. 0011 FIG. 3);
forming a plurality of nanostructures (“first nanostructures 52A-C” and “second nanostructures 54”, para. 0021) over the fin and arranged in a vertical direction;
forming shallow trench isolation (STI) regions (“shallow trench isolation (STI) regions 68” para. 0024 FIG. 4) surrounding the fin;
forming a hard mask structure (“first spacer layer 80” and “second spacer layer 82” para. 0034 FIG. 7A) on the STI regions;
forming a gate structure (“gate dielectric layer 100” and “gate electrode 102”, para. 0074 FIG. 29A-29B) wrapping around the plurality of nanostructures and on the hard mask structure; and
depositing an interlayer dielectric (ILD) layer (“first interlayer dielectric (ILD) 96” para. 0069 FIG. 25A-25C) surrounding the gate structure and over the hard mask structure.
Regarding claim 22, Huang teaches the method of claim 21, wherein the hard mask structure is a multilayer structure (“multilayer insulation film 130” comprises a “first film 131”, “second film 132”, and “third film 133”, para. 0075).
Regarding claim 24, Huang teaches the method of claim 21, wherein forming the hard mask structure on the STI regions comprises:
forming a first hard mask layer (“first film 131” para. 0075) over the STI regions; and
forming a second hard mask layer (“second film 132”, para. 0075) over the first hard mask layer, wherein the second hard mask layer has a material different from a material of the first hard mask layer (“first film 131” is silicon oxide while “second film 132” is silicon nitride).
Regarding claim 25, Huang teaches the method of claim 21, wherein the second hard mask layer is a nitride layer (“second film 132” is silicon nitride).
Claim(s) 21-22 and 24-25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Park et al. US 20190115424 A1 (hereinafter referred to as Park).
Regarding claim 21, Park teaches
A method (“method of manufacturing a semiconductor device” para. 0063 FIG. 3-16), comprising:
forming a fin (“projection portion 104”, para. 0069 FIG. 4) protruding from a substrate (“substrate 101” with “first semiconductor layers 111 and the second semiconductor layers 112” para. 0065 FIG. 4);
forming a plurality of nanostructures (“first semiconductor patterns 151” and “second semiconductor patterns 152”, para. 0071) over the fin and arranged in a vertical direction (“first semiconductor patterns 151” and “second semiconductor patterns 152” are vertically arranged on “projection portion 104”);
forming shallow trench isolation (STI) regions (“separation insulating layer 105” para. 0069) surrounding the fin;
forming a hard mask structure (“multilayer insulation film 130′” para. 0074) on the STI regions;
forming a gate structure (“non-active electrode NG” para. 0110 FIG. 15-15B) wrapping around the plurality of nanostructures and on the hard mask structure; and
depositing an interlayer dielectric (ILD) layer (“separation insulating layer ISO” para. 0120 FIG. 16) surrounding the gate structure and over the hard mask structure (“separation insulating layer ISO” is formed over “non-active electrode NG” and “multilayer insulation film 130).
Regarding claim 22, Park teaches the method of claim 21, wherein the hard mask structure is a multilayer structure (“multilayer insulation film 130” comprises a “first film 131”, “second film 132”, and “third film 133”, para. 0075).
Regarding claim 24, Park teaches the method of claim 21, wherein forming the hard mask structure on the STI regions comprises:
forming a first hard mask layer (“first film 131” para. 0075) over the STI regions; and
forming a second hard mask layer (“second film 132”, para. 0075) over the first hard mask layer, wherein the second hard mask layer has a material different from a material of the first hard mask layer (“first film 131” is silicon oxide while “second film 132” is silicon nitride).
Regarding claim 25, Park teaches method of claim 21, wherein the second hard mask layer is a nitride layer (“second film 132” is silicon nitride).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. US 20190115424 A1 (hereinafter referred to as Park), in view of Wan et al. US 20220037505 A1 (hereinafter referred to as Wan).
Regarding claim 1, Park teaches
A method (“method of manufacturing a semiconductor device” para. 0063 FIG. 3-16), comprising:
patterning a substrate (“substrate 101” with “first semiconductor layers 111 and the second semiconductor layers 112” para. 0065 FIG. 4) to form a fin (a “first fin structure AP1” comprising “first semiconductor patterns 151” and “second semiconductor patterns 152” and a “projection portion 104”, para. 0068-0071 FIG. 4) protruding from the substrate, wherein the fin has a first portion (“projection portion 104”), a second portion over the first portion (lowermost “first semiconductor pattern 151”), and a third portion over the second portion (lowermost “second semiconductor portion 152”);
forming shallow trench isolation (STI) regions (“separation insulating layer 105” para. 0069) over the substrate and surrounding the first portion of the fin (“separation insulating layer 105” is formed around “projection portion 104”, para. 0069);
forming a hard mask structure (“multilayer insulation film 130′” para. 0074) over the STI regions and surrounding the second portion of the fin (“multilayer insulation film 130′” is formed conformally on “first fin structure AP1” para. 0074), wherein the hard mask structure includes a first dielectric material (“second film 132” in “multilayer insulation film 130′” comprises silicon nitride, para. 0074)
forming a gate structure (“non-active electrode NG” para. 0110 FIG. 15-15B) on the hard mask structure and across the fin.
However, Park fails to teach the first dielectric material different from a dielectric material of the STI region.
Nevertheless, shallow trench isolations are made of many different materials, such as silicon oxide, silicon nitride, silicon oxynitride, or others as indicated in Wan. Either material is obvious to try and results in an isolation structure; it may be the same as the silicon nitride “second film 132” or may be different by using silicon oxide. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that silicon oxide is a known material suitable for use as “separation insulating layers 105”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught in Park with the shallow trench isolation material as taught in Wan. Silicon oxide is a material suitable for use in shallow trench isolations.
Regarding claim 2, Park, modified by Wan, teach the method of claim 1, wherein forming the hard mask structure comprises:
forming a first hard mask layer (“first film 131”) of a second dielectric material (“first film 131” comprises silicon oxide, para. 0075) over the fin; and
forming a second hard mask layer (“second film 132”) of the first dielectric material over the first hard mask layer, wherein the second dielectric material is different from the first dielectric material (“first film 131” is silicon oxide while “second film 132” is silicon nitride).
Regarding claim 3, Park, modified by Wan, teach the method of claim 2, wherein the second dielectric material comprises silicon oxide (“first film 131” is silicon oxide), and the first dielectric material comprises silicon nitride (“second film 132” and “separation insulating layers 105” as modified are silicon nitride).
Regarding claim 4, Park, modified by Wan, teach the method of claim 2, wherein the first hard mask layer has a U-shape when viewed from a cross-sectional view (“first film 131” has an inverted U-shape in FIG. 15B).
Allowable Subject Matter
Claims 8-15 allowed.
The following is an examiner’s statement of reasons for allowance:
The most relevant prior art Huang fails to teach depositing a bottom anti-reflective coating (BARC) layer on the second hard mask layer; performing a planarization process to planarize the BARC layer and the second hard mask layer; removing the BARC layer. Therefore, claim 8 is considered allowable.
Claims 9-15 are allowed based on their dependency on claim 8.
Claims 5-6 and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5, the most relevant prior art Huang teaches an IDL layer on the hard mask structure and the gate structure but the ILD layer does not contact the ILD layer. They are interposed by an etch stop layer. Therefore, claim 5 is considered to contain allowable subject matter.
Regarding claim 6, Huang fails to teach depositing a bottom anti-reflective coating (BARC) layer on the second hard mask layer; performing a planarization process to planarize the BARC layer and the second hard mask layer; removing the BARC layer. Therefore, claim 8 is considered allowable.
Regarding claim 23, Huang and Park teach hardmask layers having upper surfaces higher than a bottom surface of the bottommost one of the plurality of nanostructures. Therefore, claim 23 is considered to contain allowable subject matter.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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