DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-7, 15-27 are pending. Claims 3, 5, 6, 19, 20 are withdrawn. Claims 8-14 are cancelled. Claims 21-27 are new.
Election/Restrictions
Applicant’s election without traverse of Group I, drawn to the method of manufacturing in the reply filed on June 15, 2026 is acknowledged.
Applicant’s election without traverse of Species 4, [0125] a thermal oxidation technique is used to perform the oxidation operation 1025. The thermal oxidation technique may include a baking operation in which the p-type metal layer 1015 is exposed to elevated temperatures for a time duration to promote oxidation of the surface of the p-type metal layer 1015. The p-type metal layer 1015 may be exposed to atmospheric gasses that contain oxygen during the baking operation such that the oxygen in the atmospheric gasses, in combination with the elevated temperatures, results in the oxidation of the surface of the p-type metal layer 1015, in the reply filed on June 15, 2026 is acknowledged.
Claims 3, 5, 6, 19, 20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 15, 2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 8, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1, 2, 7 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (U.S. 2023/0395435), and Basker et al (U.S. 2015/0279839).
Regarding claim 1. Lee et al discloses a method, comprising:
forming a first plurality of nanostructure (FIG. 13B, item 210A) channel layers (FIG. 13B, item 214) that are arranged in a direction (FIG. 13B, item Z) that is approximately perpendicular ([0018]) to a semiconductor substrate (FIG. 13B, item 202) of a semiconductor device (FIG. 13B, item 200);
forming a second plurality of nanostructure (FIG. 13B, item 210B) channel layers (FIG. 13B, item 214) that are arranged in the direction (FIG. 13B, item Z) that is approximately perpendicular ([0018]) to the semiconductor substrate (FIG. 13B, item 202);
forming a first type metal layer (FIG. 13B, item 290b) wrapping around each of the first plurality of nanostructure (FIG. 13B, item 210A) channel layers (FIG. 13B, item 214);
forming a metal oxide layer ([0041], i.e. The diffusion of oxygen atoms into the second n-type WF layer 290b increases Vt of an NFET by causing n-type WF metal oxidation) on the first type metal layer (FIG. 13B, item 290b); and
forming a second type metal layer (FIG. 13B, item 294) on the metal oxide layer ([0041], i.e. The diffusion of oxygen atoms into the second n-type WF layer 290b increases Vt of an NFET by causing n-type WF metal oxidation) and on the second plurality of nanostructure (FIG. 13B, item 210B) channel layers (FIG. 13B, item 214).
Lee et al fails to explicitly disclose wherein a first thickness of the second type metal layer on the metal oxide layer is different from a second thickness of the second type metal layer on the second plurality of nanostructure channel layers.
However, Basker et al teaches a first thickness of the second type metal layer on the metal oxide layer is different from a second thickness of the second type metal layer on the second plurality of nanostructure channel layers ([0020], i.e. a first portion 122 of the second WFM layer 120 surrounding the isolated semiconductor fin 102′ has a thickness (d.sub.WFM1) that is different than a thickness (d.sub.WFM2) of second portion 124 of the second WFM layer 120 surrounding the remaining semiconductor fins 102. That is, the pitch variation between the isolated semiconductor fin 102′ and the remaining semiconductor fins 102 generates a thickness differential (Δd.sub.WFM) with respect to the first portion 122 of the second WFM layer 120 the second portion 124 of the second WFM 120).
Since Lee et al and Basker et al teach multi-gate semiconductor devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the first thickness of the second type metal layer on the metal oxide layer is different from a second thickness of the second type metal layer on the second plurality of nanostructure channel layers as disclosed to modify Lee et al with the teachings of a thickness differential (Δd.sub.WFM) with respect to the first portion of the second WFM layer the second portion of the second WFM as disclosed by Basker et al. The use of the thickness differential (Δd.sub.WFM) of the second WFM layer in Basker et al provides for a variation in the threshold voltage (Vt) between one or more isolated semiconductor fins and one or more of the remaining semiconductor fins (Basker et al, [0020]).
Regarding claim 2. Lee et al and Basker et al discloses all the limitations of the method of claim 1 above.
Lee et al further discloses wherein forming the metal oxide layer comprises oxidizing a surface of the first type metal layer to form the metal oxide layer ([0042])
Regarding claim 7. Lee et al and Basker et al discloses all the limitations of the method of claim 1 above.
Lee et al wherein the first type metal layer comprises a titanium nitride (TixNy) ([0042]); and wherein the metal oxide layer comprises a titanium oxide (TiOx) ([0042])
Allowable Subject Matter
Regarding claim 4. Claim 4 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 15-18, 21-27 are allowable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee et al (U.S. 2024/0014279) discloses SEMICONDUCTOR DEVICE AND FORMATION METHOD THEREOF
Chanemougame et al (U.S. 10566248) disclose Work Function Metal Patterning For N-P Spaces Between Active Nanostructures Using Unitary Isolation Pillar
Chu et al (U.S. 2022/0320089) discloses MULTIPLE PATTERNING GATE SCHEME FOR NANOSHEET RULE SCALING
Chen et al (U.S. 2023/0063857) discloses INTEGRATED CIRCUIT DEVICE WITH IMPROVED RELIABILITY
Mun et al (U.S. 2021/0013110) discloses METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING A PLURALITY OF CHANNEL PATTERNS
Bao et al (U.S. 2020/0043808) discloses GATE-ALL-AROUND FETS HAVING UNIFORM THRESHOLD VOLTAGE
(U.S. 2023/0268409) discloses STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH METAL GATE
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT E BAUMAN whose telephone number is (469)295-9045. The examiner can normally be reached M-F, 9-5 CST.
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/S.E.B./Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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