DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/21/2024 and 03/14/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of species II in the reply filed on 04/10/2026 is acknowledged.
Claims 3-7 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/10/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by US PG Patent No. 6,924,701 to Bhandari (hereinafter Bhandari).
Regarding Claim 1, Bhandari discloses a structure including:
a bipolar junction transistor (128, Fig. 1A) including:
a base region (b) connected to an input node (Inp); and
a collector region (c); and
a field effect transistor (122) including:
a source region (s) connected to the collector region (via node 126); and
a drain region (d) connected to an output node (106, Outp).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 8-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bhandari in view of US PG Pub 2012/0319758 to Kobayashi et al (hereinafter Kobayashi).
Regarding Claim 2, Bhandari discloses the structure of Claim 1 but does not disclose the devices being on different chips.
Kobayashi discloses a first chip (44, Fig. 1) with a FET device having a source (22) connected to a collector (38) of a BJT (28) located on a second chip (42).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the devices of Bhandari to be on different chips, stacked upon each other. Forming the devices on different substrates would have provided obvious benefits such as the inclusion of other passive or active devices and/or utilizing different materials that better enhance operations of the respective devices.
Regarding Claim 8, Bhandari discloses a structure including:
a bipolar junction (128, Fig. 1A) transistor on a first chip, wherein the bipolar junction transistor includes a base region (b) connected to an input node (Inp) and a collector region (c); and
a field effect transistor (122) on a second chip, wherein the second chip is stacked on the first chip and wherein the field effect transistor includes:
a source region (s) connected to the collector region (via node 126) and
a drain region (d) connected to an output node (Outp).
Bhandari does not disclose the devices being on different chips.
Kobayashi discloses a first chip (44, Fig. 1) with a FET device having a source (22) connected to a collector (38) of a BJT (28) located on a second chip (42).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the devices of Bhandari to be on different chips, stacked upon each other. Forming the devices on different substrates would have provided obvious benefits such as the inclusion of other passive or active devices and/or utilizing different materials that better enhance operations of the respective devices.
Regarding Claim 9, the combination of Bhandari and Kobayashi makes obvious the structure of Claim 8, wherein the first chip includes first metal levels and the second chip includes second metal levels adjacent to the first metal levels,
wherein the structure further includes passive elements, and
wherein at least some of the passive elements are in the first metal levels and the second metal levels between the bipolar junction transistor and the field effect transistor.
Both Bhandari and Kobayashi make use of passive devices (Bhandari, Fig. 1A; Kobayashi, Fig. 5). Forming these devices in either chip among the metal levels within the circuits would have been an obvious design choice for one of ordinary skill in the art.
Regarding Claims 10, 11, 12 and 13, the combination of Bhandari and Kobayashi makes obvious the structure of Claim 9 but do not list all passive devices used by Applicant, However, passive elements such as inductors, resistors and capacitors are commonly found in the art and could have been part of numerous circuits based on the specific needs for a circuit. Applicant has not noted any unexpected or unique results outside of the specific wiring of the BJT and FET devices. Absent such results, it would have been obvious for one of ordinary skill to have included common circuit elements to achieve desired results.
Regarding Claim 14, the combination of Bhandari and Kobayashi makes obvious the structure of Claim 8, wherein the bipolar junction transistor is an NPN- type bipolar junction transistor (Bhandari, 128, Fig. 1A) and the base region includes silicon germanium and wherein the field effect transistor is a P-channel field effect transistor (Bhandari 122, Fig. 1A) with a silicon active device region.
Bhandari does not explicitly disclose the materials for the BJT or FET.
However, it would have been obvious to one of ordinary skill in the art to have formed the devices using the materials claimed by Applicant. SiGe and silicon are commonly used within the art and would have been easily selected by one of ordinary skill.
Regarding Claim 15, Bhandari discloses a structure including:
a field effect transistor (Fig. 1A, 122) on a first chip; and
a bipolar junction transistor (128) on a second chip,
wherein the second chip is stacked on the first chip (see below),
wherein the bipolar junction transistor (128) includes a base region (b) connected to an input node (Inp) and a collector region (c), and
wherein the field effect transistor (128) includes:
a source region (s) connected to the collector region (via node 126) and a drain region (d) connected to an output node (Outp).
Bhandari does not disclose the devices being on different chips.
Kobayashi discloses a first chip (44, Fig. 1) with a FET device having a source (22) connected to a collector (38) of a BJT (28) located on a second chip (42).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have modified the devices of Bhandari to be on different chips, stacked upon each other. Forming the devices on different substrates would have provided obvious benefits such as the inclusion of other passive or active devices and/or utilizing different materials that better enhance operations of the respective devices.
Regarding Claim 16, the combination of Bhandari and Kobayashi makes obvious the structure of Claim 15,
wherein the first chip includes first metal levels and the second chip includes second metal levels adjacent to the first metal levels,
wherein the structure further includes passive elements, and
wherein at least some of the passive elements are in the first metal levels and the second metal levels between the field effect transistor and the bipolar junction.
Both Bhandari and Kobayashi make use of passive devices (Bhandari, Fig. 1A; Kobayashi, Fig. 5). Forming these devices in either chip among the metal levels within the circuits would have been an obvious design choice for one of ordinary skill in the art.
Regarding Claims 17, 18 and 19, the combination of Bhandari and Kobayashi makes obvious the structure of Claim 16 but do not list all passive devices used by Applicant, However, passive elements such as inductors, resistors and capacitors are commonly found in the art and could have been part of numerous circuits based on the specific needs for a circuit. Applicant has not noted any unexpected or unique results outside of the specific wiring of the BJT and FET devices. Absent such results, it would have been obvious for one of ordinary skill to have included common circuit elements to achieve desired results.
Regarding Claim 20, the combination of Bhandari and Kobayashi makes obvious the structure of Claim 15, wherein the bipolar junction transistor is an NPN- type bipolar junction transistor (Bhandari, 128, Fig. 1A) and the base region includes silicon germanium and wherein the field effect transistor is a P-channel field effect transistor (Bhandari 122, Fig. 1A) with a silicon active device region.
Bhandari does not explicitly disclose the materials for the BJT or FET.
However, it would have been obvious to one of ordinary skill in the art to have formed the devices using the materials claimed by Applicant. SiGe and silicon are commonly used within the art and would have been easily selected by one of ordinary skill.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST.
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/DAVID C SPALLA/ Primary Examiner, Art Unit 2893
