Prosecution Insights
Last updated: October 01, 2026
Application No. 18/584,075

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

Non-Final OA §103
Filed
Feb 22, 2024
Examiner
ENAD, CHRISTINE A
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
NANYA TECHNOLOGY Corporation
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
1149 granted / 1361 resolved
+16.4% vs TC avg
Moderate +10% lift
Without
With
+10.3%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 12m
Avg Prosecution
28 currently pending
Career history
1398
Total Applications
across all art units

Statute-Specific Performance

§101
1.7%
-38.3% vs TC avg
§103
64.5%
+24.5% vs TC avg
§102
19.3%
-20.7% vs TC avg
§112
8.1%
-31.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1361 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I (Claims 1-15) in the reply filed on September 7, 2026, is acknowledged. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 3, 5, 8, 11, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lu (US Publication No. 2024/0008263) in view of Cheng (US Publication No. 2023/0118330). Regarding claims 1 and 8, Lu discloses a semiconductor memory device Fig 1B manufacturing method comprising: forming a bit line structure Fig 4, 205/206 on a substrate Fig 4, 201, wherein the bit line structure Fig 4, 205/206 comprises a bit line conductive portion Fig 4, 204 and a bit line dielectric portion Fig 4, 206; forming a silicon carbon oxide (SiCO) layer Fig 5, 207’ ¶0058 over the bit line structure Fig 5, 205/206; performing a plasma process to oxidize portions of the SiCO layer¶0063-0064; and forming a silicon nitride layer Fig 9, 209 over the bit line structure Fig 9, 205/206 and the remaining SiCO layer Fig 9, 207. Lu discloses all the limitations but silent on the etching process. Whereas Cheng discloses forming a silicon carbon oxide (SiCO) layer over a structure ¶0048; performing a hydrogen plasma process to the SiCO layer ¶0048; performing a hydrofluoric acid etching process to the SiCO layer ¶0048 Fig 5. Lu and Cheng are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lu because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the method of Lu and incorporate the teachings of Cheng to improve the etching step and manufacturing process. Regarding claims 3 and 11, Lu and Cheng disclose all the limitations but silent on the bias voltage range. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the bias voltage range, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955). It has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F. 2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F .2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F .2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F .2d 669, 149 USPQ 47 (CCPA 1966). Regarding claims 5 and 14, Lu discloses wherein the bit line dielectric portion is on a top of the bit line conductive portion Fig 6 and Fig 10. Claims 2, 4, 6-7, 9-10, 12-13, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lu (US Publication No. 2024/0008263) in view of Cheng (US Publication No. 2023/0118330) and in further view of Hong et al (US Publication No. 2021/0398569). Regarding claims 2 and 12, Lu and Cheng disclose all the limitations but silent on the etching process. Whereas Hong discloses performing a nitride etching process to the silicon nitride layer until the bit line dielectric portion is exposed ¶0129, 0132 Fig 11M. Lu and Cheng are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lu because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the method of Lu and incorporate the teachings of Cheng to improve the etching step and provide a contact region. Regarding claims 4 and 9, Hong discloses wherein the SiCO layer consists of 37% silicon, 48% oxygen and 15% carbon ¶0042. Regarding claims 6 and 15, Hong discloses wherein the bit line conductive portion comprises a tungsten portion, a polysilicon portion, and a diffusion barrier layer between the tungsten portion and the polysilicon portion ¶0030-0031. Regarding claims 7 and 13, Hong discloses wherein a top end of the remaining SiCO layer is fully enclosed by the bit line dielectric portion and the remaining silicon nitride layer that is not etched by the nitride etching process Fig 11M. Regarding claim 10, Lu and Cheng disclose all the limitations but silent on the silicon/oxygen composition. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the specific oxygen/silicon composition, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ (CCPA 1980). It has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F. 2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F .2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F .2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F .2d 669, 149 USPQ 47 (CCPA 1966). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTINE A ENAD whose telephone number is (571)270-7891. The examiner can normally be reached Monday-Friday, 7:30 am -4:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571 272 1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

Feb 22, 2024
Application Filed
Sep 21, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
95%
With Interview (+10.3%)
1y 12m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1361 resolved cases by this examiner. Grant probability derived from career allowance rate.

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