CTNF 18/584,165 CTNF 89654 DETAILED ACTION This application, 18/584165, attorney docket 891102.500, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This application is assigned to Taiwan Semiconductor Manufacturing Co., Ltd., and has an effective filing date of 2/22/2024 . Applicant's election without traverse of Group I, claims 15-20 in the reply filed on 7/30/2025 is acknowledged. Claims 1-14 have been cancelled and claims 21-34 have been added by the applicant. Claims 15-34 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-aia AIA Claim s 15-17 and claim 20 are rejected under 35 U.S.C. 102 a1/a2 as being anticipated by Young et al. (U.S. 2021/0375990) . As for claim 15, Young teaches in figures 8a-18b a method, comprising: forming a device layer (106a) on a substrate (102); forming a first portion of an interconnect structure on the device layer (130a, fig. 9b); forming a resistive random access memory (RRAM) device “… an arrangement of such memory cells 108 manufactured storage device 100 is referred to as a resistive random access memory (ReRAM) device.” [0023] on the first portion, including: forming an oxide semiconductor layer (For example, the channel layer can be made of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium tin oxide or indium titanium oxide (ITO) or another oxide semiconductor material” [0023]; forming a gate structure (124/132) that wraps around the oxide semiconductor layer (figure 14a, 14c); and forming a resistor (108), the resistor and the oxide semiconductor layer being stacked in a vertical direction (shown in figure 15c); and forming a second portion of the interconnect structure (116, figure 16B) on the RRAM device. As for claim 16, Young teaches the method of claim 15, and teaches that the forming a resistor is after the forming an oxide semiconductor layer (formed on existing channel in figure 10B). As for claim 17 , Young teaches the method of claim 15, wherein the forming a resistor includes: forming a bottom electrode on the oxide semiconductor layer; forming a switching layer on the bottom electrode; and forming a top electrode on the switching layer. “The storage cell 108 can be a lower electrode 110 , one above the lower electrode 110 arranged data storage structure 112 and one above the data storage structure 112 arranged upper electrode 114 …[0023]. As for claim 20, Young teaches the method of claim 15, wherein the forming a first portion of an interconnect structure is forming the first portion of a back side interconnect structure (132), the method further including: forming a front side interconnect structure (layers 106b-106c) prior to the forming a first portion of an interconnect structure . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim s 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Young in view of Hashim et al. ( U.S. 10,374,039) . As for claim 18 , Young teaches the method of claim 17, but does not teach that forming a resistor includes forming the bottom electrode, the switching layer and the top electrode having a sharp-tipped profile in cross-sectional side view. However, Hashemi teaches in figure 6, forming the bottom electrode, the switching layer and the top electrode having a sharp-tipped profile in cross-sectional side view. It would have been obvious to one skilled in the art at the effective filing date of this application to use the VR shape of Hashemi to concentrate the current (Hashimi [co7 ln26]). One skilled in the art would have combined these elements with a reasonable expectation of success. As for claim 19, Young teaches the method of claim 17, but does not teach that the forming a resistor includes forming the bottom electrode, the switching layer and the top electrode having an M-shaped profile in cross-sectional side view. However, Hashemi teaches in figure 6 forming the bottom electrode, the switching layer and the top electrode having an M-shaped profile in cross-sectional side view. It would have been obvious to one skilled in the art at the effective filing date of this application to use the VR shape of Hashemi to concentrate the current (Hashimi [co7 ln26]). One skilled in the art would have combined these elements with a reasonable expectation of success . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 21-34 are allowed. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: As for claim 21, Young teaches a method, comprising: forming a device layer (106a) on a substrate (102); forming a first portion of an interconnect structure (1360a) on the device layer; forming a resistive random access memory (RRAM) device on the first portion, including: forming a resistor in an opening in a dielectric layer of the first portion; forming an oxide semiconductor layer on the resistor; and forming a gate structure that wraps around the oxide semiconductor layer; and forming a second portion of the interconnect structure on the RRAM device. The prior art does not teach of make obvious building the RRAM device in an opening a dielectric, first forming a resistor, then an oxide semiconductor on the resistor, then a gate wrapping around the oxide semiconductor. Claims 22-26 depend from claim 21 and include the same sequence of method steps. As for claim 27, The prior art does not teach or make obvious a method of making an RRAM device including forming a back side interconnect structure on a back side of the device layer opposite the front side, including forming a first power rail that connects to the source/drain of the transistor; and forming a resistive random-access memory (RRAM) device, and forming a fused device, the fused device and the oxide semiconductor layer being stacked in a vertical direction. Claim 28-34 depend from claim 27 and include the same novel method . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN A BODNAR whose telephone number is (571)272-4660. The examiner can normally be reached M-Th and every other Friday 7:30-5:30 Central time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOHN A BODNAR/ Primary Examiner, Art Unit 2893 Application/Control Number: 18/584,165 Page 2 Art Unit: 2893 Application/Control Number: 18/584,165 Page 3 Art Unit: 2893 Application/Control Number: 18/584,165 Page 4 Art Unit: 2893 Application/Control Number: 18/584,165 Page 5 Art Unit: 2893 Application/Control Number: 18/584,165 Page 6 Art Unit: 2893 Application/Control Number: 18/584,165 Page 7 Art Unit: 2893
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