Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to the independent claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 15, 25, 17, 19, 34, 39, 41, 45, 50, 58, 60, 68 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (hereinafter Chiu, US 2024/0096740) in view of Kang et al. (hereinafter Kang, US 2020/0144237).
In regards to independent claim 1, Chiu teaches a semiconductor device package, comprising:
a submount (162) (Chiu, Fig. 3A);
a thermoelectric structure (110) on the submount (162), the thermoelectric structure (110) operable to adjust a temperature difference between a first side of the thermoelectric structure and a second side of the thermoelectric structure based on a bias voltage applied to the thermoelectric structure (“It should be noted that when the voltage is applied across the thermoelectric cooler 610, a temperature gradient is formed between the top surface and the bottom surface of the thermoelectric cooler 610,” Chiu, [0067]); and
one or more semiconductor die (100) on the thermoelectric structure (110) (Chiu, Fig. 2).
Chiu fails to explicitly teach:
a die-attach material coupling the one or more semiconductor die to the first side of the
thermoelectric structure.
Kang teaches:
a die-attach material coupling the one or more semiconductor die to the first side of the
thermoelectric structure (Kang, 125, [0083]).
It would have been obvious to one of ordinary skill in the art, having the teachings of Chiu and Kang before him before the effective filing date of the claimed invention, to modify the thermoelectric semiconductor structures taught by Chiu to include the die attach film of Kang in order to obtain thermoelectric semiconductor structures that attaches using die attach film. One would have been motivated to make such a combination because it improves heat transfer from the semiconductor to the thermoelectric device.
In regards to dependent claim 15, Chiu teaches wherein the thermoelectric structure comprises a plurality of p-type thermoelectric semiconductor structures (112, P) and a plurality of n-type thermoelectric semiconductor structures (114, N) (Chiu , Fig. 3A).
In regards to dependent claim 25, Chiu teaches a power substrate (132) between the thermoelectric structure (110) and the one or more semiconductor die (100), wherein:
the power substrate (132) comprises a first conducting layer, a second conducting layer (134, shows three layers), and an insulating layer (136) between the first conducting layer and the second conducting layer, and
the one or more semiconductor die are on the power substrate (100) (Chiu , Fig. 2).
In regards to dependent claim 27, Chiu teaches wherein the submount is a first submount (162), wherein the one or more semiconductor die (100) comprises a plurality of semiconductor die ([0028]), the semiconductor device package further comprising:
a second submount (132) on the first side of the thermoelectric structure (110),
wherein the plurality of semiconductor die (100) are on the second submount (132) (Chiu , Fig. 2).
In regards to dependent claim 29, Chiu teaches wherein the thermoelectric structure is a first thermoelectric structure, the semiconductor device package further comprising a second thermoelectric structure on a side of the one or more semiconductor die opposite from the first thermoelectric structure (Chiu, [0067], Fig. 6, Item 110, 610).
In regards to dependent claim 34, Chiu teaches wherein the semiconductor device package is one of a discrete semiconductor package (P1) or a power module (Chiu Fig. 2, [0028]).
In regards to independent claim 39, Chiu teaches a semiconductor device package, comprising:
a thermoelectric structure (110) comprising an array of thermoelectric semiconductor structures (112, 114); and
a semiconductor die (100) on the thermoelectric structure (110) (Chiu, Fig. 2, Fig. 3A).
Chiu fails to explicitly teach:
a die-attach material coupling the one or more semiconductor die to the first side of the
thermoelectric structure.
Kang teaches:
a die-attach material coupling the one or more semiconductor die to the first side of the
thermoelectric structure (Kang, 125, [0083]).
It would have been obvious to one of ordinary skill in the art, having the teachings of Chiu and Kang before him before the effective filing date of the claimed invention, to modify the thermoelectric semiconductor structures taught by Chiu to include the die attach film of Kang in order to obtain thermoelectric semiconductor structures that attaches using die attach film. One would have been motivated to make such a combination because it improves heat transfer from the semiconductor to the thermoelectric device.
In regards to dependent claim 41, Chiu teaches wherein the thermoelectric structure (110) comprises a first layer (180) defining a first side of the thermoelectric structure (110) and a second layer (170) defining a second side of the thermoelectric structure (110), and wherein the array of thermoelectric semiconductor structures (112, 114) is between the first layer (180) and the second layer (170) (Chiu, Fig. 2, Fig. 3A).
In regards to dependent claim 45, Chiu teaches a plurality of interconnects (116) coupling adjacent thermoelectric semiconductor structures in the array (112, 114), the plurality of interconnects (116) comprising one or more first interconnects (116) contacting the first layer (180) and one or more second interconnects (116) contacting the second layer (170),
wherein each thermoelectric semiconductor structure (110) comprises a first side (180) and an opposing second side (170), each of the first interconnects (116) contacting a respective first side (180) and each of the second interconnects (116) contacting a respective second side (170) (Chiu, Fig. 2, Fig. 3A).
In regards to dependent claim 50, Chiu teaches wherein the thermoelectric structure further comprises a first bias voltage connection structure coupled to a first end of the array and a second bias voltage connection structure coupled to a second end of the array (Chiu, [0026]), and
wherein the array comprises a plurality of p-type thermoelectric semiconductor structures and a plurality of n-type thermoelectric semiconductor structures, the plurality of p-type thermoelectric semiconductor structures being alternately arranged in series with the plurality of n-type thermoelectric semiconductor structures between the first end of the array and the second end the array (Chiu, Fig. 3A, 112, 114).
In regards to independent claim 58, Chiu teaches a semiconductor device package, comprising:
a housing (135, underfill acts as a housing for 110);
a submount (162);
a thermoelectric structure (110);
at least one connection structure (138, 178) extending from the housing (135), the at least one connection structure (178) coupled to the thermoelectric structure (110); and
at least one semiconductor die (100) on the thermoelectric structure (110) (Chiu, Fig. 2).
Chiu fails to teach:
at least one connection structure extending outward from the housing.
Kang teaches:
at least one connection structure extending outward from the housing (Kang, 220 in housing 200, 230, with connection structures 265 extending outward).
It would have been obvious to one of ordinary skill in the art, having the teachings of Chiu and Kang before him before the effective filing date of the claimed invention, to modify the thermoelectric semiconductor structures taught by Chiu to include the outer connection structures of Kang in order to obtain thermoelectric semiconductor structures that attaches using outer connection balls. One would have been motivated to make such a combination because it allow the thermoelectric device and the semiconductor die to be manufactured separately and then attached at a separate time or location.
In regards to dependent claim 60, Chiu teaches wherein the at least one connection structure is one of a pin, a lead, a terminal, a contact, an interconnect, or a bonding pad ([0037], 178, Chiu, Fig. 2).
In regards to dependent claim 68, Chiu teaches a heat sink coupled to the thermoelectric structure, wherein the heat sink comprises a thermally conductive material (Chiu, [0022], [0080]).
Claim(s) 17, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu in view of Kang and Satoh et al. (hereinafter Satoh, UC 2020/0161525).
In regards to dependent claim 17, Chiu teaches the semiconductor device package of claim 15. Chiu fails to explicitly teach wherein the plurality of p-type thermoelectric semiconductor structures and the plurality of n-type thermoelectric semiconductor structures comprise a bismuth alloy. Satoh teaches wherein the plurality of p-type thermoelectric semiconductor structures and the plurality of n-type thermoelectric semiconductor structures comprise a bismuth alloy (Satoh, [0068]). It would have been obvious to one of ordinary skill in the art, having the teachings of Chiu and Satoh before him before the effective filing date of the claimed invention, to modify the thermoelectric semiconductor structures taught by Chiu to include the bismuth alloy of Satoh in order to obtain thermoelectric semiconductor structures that utilize bismuth alloy. One would have been motivated to make such a combination because it provides low toxicity, high electrical conductivity combined with low thermal conductivity.
In regards to dependent claim 19, Chiu teaches the semiconductor device package of claim 15. Chiu fails to explicitly teach wherein the plurality of p-type thermoelectric semiconductor structures and the plurality of n-type thermoelectric semiconductor structures comprise a conductive polymer, the conductive polymer being one of poly polystyrene sulfonate (PEDOT:PSS), polyaniline (PANI), polythiophene (PTH), or polyphenylene vinylene (PPV). Satoh teaches wherein the plurality of p-type thermoelectric semiconductor structures and the plurality of n-type thermoelectric semiconductor structures comprise a conductive polymer, the conductive polymer being one of poly polystyrene sulfonate (PEDOT:PSS), polyaniline (PANI), polythiophene (PTH), or polyphenylene vinylene (PPV) (Satoh, [0094]). It would have been obvious to one of ordinary skill in the art, having the teachings of Chiu and Satoh before him before the effective filing date of the claimed invention, to modify the thermoelectric semiconductor structures taught by Chiu to include the polyaniline of Satoh in order to obtain thermoelectric semiconductor structures that utilize polyaniline. One would have been motivated to make such a combination because it provides low cost, low thermal conductivity, high flexibility, excellent environmental stability, and ease of processing.
Claim(s) 52 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu in view of Kang and Tsai et al. (hereinafter Tsai, US 2025/0218892).
In regards to dependent claim 52, Chiu teaches the semiconductor device package of claim 50. Chiu fails to explicitly teach wherein each of the plurality of p-type thermoelectric semiconductor structures comprises bismuth telluride doped with antimony, and each of the plurality of n-type thermoelectric semiconductor structures comprises bismuth telluride doped with selenium. Tsai teaches wherein each of the plurality of p-type thermoelectric semiconductor structures comprises bismuth telluride doped with antimony, and each of the plurality of n-type thermoelectric semiconductor structures comprises bismuth telluride doped with selenium (Tsai, [0028]). It would have been obvious to one of ordinary skill in the art, having the teachings of Chiu and Tsai before him before the effective filing date of the claimed invention, to modify the thermoelectric semiconductor structures taught by Chiu to include the bismuth semiconductors of Tsai in order to obtain thermoelectric semiconductor structures that utilizes bismuth. One would have been motivated to make such a combination because it provides low toxicity, high electrical conductivity combined with low thermal conductivity.
Claim(s) 55 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu in view of Kang and Song et al. (hereinafter Song, Polymer/carbon nanotube composite materials for flexible thermoelectric power generator).
In regards to dependent claim 55, Chiu teaches the semiconductor device package of claim 50. Chiu fails to explicitly teach wherein each of the plurality of p-type thermoelectric semiconductor structures comprises a PEDOT-carbon nanotube (CNT) composite, and each of the plurality of n-type thermoelectric semiconductor structures comprises a polyethylenimine (PEI) doped PEDOT-carbon nanotube (CNT) composite. Song teaches wherein each of the plurality of p-type thermoelectric semiconductor structures comprises a PEDOT-carbon nanotube (CNT) composite, and each of the plurality of n-type thermoelectric semiconductor structures comprises a polyethylenimine (PEI) doped PEDOT-carbon nanotube (CNT) composite (Song, abstract). It would have been obvious to one of ordinary skill in the art, having the teachings of Chiu and Song before him before the effective filing date of the claimed invention, to modify the thermoelectric semiconductor structures taught by Chiu to include the PEDOT-carbon nanotube (CNT) composite of Song in order to obtain thermoelectric semiconductor structures that utilizes PEDOT-carbon nanotube (CNT) composite. One would have been motivated to make such a combination because it has has intrinsic low thermal conductivity and are close to phonon glasses which capitalizes on the intrinsic strengths of conducting polymers and inorganic nanostructures or carbon nanomaterials for thermoelectric applications and/or use the interfacial effects to enhance the thermoelectric performance exceeding that of the individual components
Claim(s) 42, 49 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu and Kang
In regards to dependent claim 42, Chiu teaches the semiconductor device package of claim 41. Chiu fails to explicitly teach wherein the thermoelectric structure comprises a thermoelectric film, each of the first layer and the second layer having a thickness in a range of about 0.3 microns to about 5 microns.
Differences in the thicknesses will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such thicknesses are critical. Thickness is a result-effective variable. Reducing the thickness decreases the size of the device which will allow more devices on a chip thereby would enable the design need of increased computing power of the device. Therefore the thickness would be obtainable by routine experimentation. "Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation." See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955). Further, “It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.” See In re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929). "When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under §103.” See KSR International Co. v. Teleflex Inc., 550 U.S. at 421, 82 USPQ2d at 1397
Criticality Since the applicant has not established the criticality of the thicknesses and similar thicknesses are known in the art, it would have been obvious to one of the ordinary skill in the art to use these values in the device of King. The specification contains no disclosure of either the critical nature of the claimed thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
In regards to dependent claim 49, Chiu teaches the semiconductor device package of claim 39. Chiu fails to explicitly teach wherein each semiconductor structure in the array has a thickness in a range of about 0.1 microns to about 20 microns, a length in a range of about 1 micron to about 1000 microns, a width in a range of about 1 micron to about 1000 microns, and is separated from adjacent thermoelectric semiconductor structures in the array by a distance in a range of about 1 micron to about 100 microns. Differences in the thicknesses will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such thicknesses are critical. Thickness is a result-effective variable. Reducing the thickness decreases the size of the device which will allow more devices on a chip thereby would enable the design need of increased computing power of the device. Therefore the thickness would be obtainable by routine experimentation. "Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation." See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955). Further, “It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.” See In re Williams, 36 F.2d 436, 438, 4 USPQ 237 (CCPA 1929). "When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under §103.” See KSR International Co. v. Teleflex Inc., 550 U.S. at 421, 82 USPQ2d at 1397
Criticality Since the applicant has not established the criticality of the thicknesses and similar thicknesses are known in the art, it would have been obvious to one of the ordinary skill in the art to use these values in the device of King. The specification contains no disclosure of either the critical nature of the claimed thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
Claim(s) 73 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu in view of Kang and Namuduri et al. (hereinafter Namuduri, US 2024/0234238).
In regards to dependent claim 73, Chiu teaches the semiconductor device package of claim 39. Chiu fails to explicitly teach wherein the at least one semiconductor die comprises at least one wide bandgap semiconductor device, the at least one wide bandgap semiconductor device comprising one of a silicon carbide-based metal-oxide-semiconductor field-effect transistor (MOSFET), a silicon carbide-based Schottky diode, or a Group-III nitride-based high electron mobility transistor (HEMT) device.
Namuduri teaches wherein the at least one semiconductor die comprises at least one wide bandgap semiconductor device, the at least one wide bandgap semiconductor device comprising one of a silicon carbide-based metal-oxide-semiconductor field-effect transistor (MOSFET), a silicon carbide-based Schottky diode, or a Group-III nitride-based high electron mobility transistor (HEMT) device (Namuduri, [0005]). It would have been obvious to one of ordinary skill in the art, having the teachings of Chiu and Song before him before the effective filing date of the claimed invention, to modify the thermoelectric semiconductor structures taught by Chiu to include the silicon carbide-based metal-oxide-semiconductor field-effect transistor composite of Song in order to obtain thermoelectric semiconductor attached to a silicon carbide-based metal-oxide-semiconductor field-effect transistor. One would have been motivated to make such a combination because it enables the thermoelectric structure to be used in high density systems like in electric vehicles (EVs) and hybrid electric vehicles (HEVs) to control and power systems in industrial, marine, aerospace, locomotive, and utility applications.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM C TRAPANESE whose telephone number is (571)270-3304. The examiner can normally be reached Monday - Friday 7am-12pm & 8pm-10pm EST.
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/WILLIAM C TRAPANESE/Primary Examiner, Art Unit 2812
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