DETAILED ACTION
Claims 1-20 are pending before the Office for review.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 6-13 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over YOO et al (US Patent Application Publication 2021/0035854) in view of AUSTIN et al (WO 2021/202808).
With regards to claims 1 and 12, Yoo discloses a semiconductor processing method comprising: providing a silicon-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is housed in the processing region, wherein the substrate defines a feature, forming plasma effluents of the silicon-containing precursor; providing an oxygen-containing precursor to the processing region of the semiconductor processing chamber; forming plasma effluents of the oxygen-containing precursor; forming a silicon and oxygen containing material (silicon oxide) wherein the contacting forms a silicon-and-oxygen-containing material; providing a fluorine-containing precursor to the processing region of the semiconductor processing chamber; forming plasma effluents of the fluorine-containing precursor; and contacting the silicon-and-oxygen-containing material (silicon oxide) with plasma effluents of the fluorine-containing precursor, wherein the contacting etches the silicon-and-oxygen-containing material from a top, a sidewall, or both of the feature. (Paragraphs [0039]-[0048], [0053], Figures 3-4 discloses removing material 41 from the top and sidewall).
Yoo does not explicitly disclose wherein the processing region is at least partially defined between a faceplate and a substrate support on which the substrate is seated; forming plasma effluents of the silicon-containing precursor; depositing a silicon-containing material on the substrate; providing an oxygen-containing precursor to the processing region of the semiconductor processing chamber; forming plasma effluents of the oxygen-containing precursor; contacting the silicon-containing material with the plasma effluents of the oxygen-containing precursor to oxidize the silicon-containing material, wherein the contacting forms a silicon-and-oxygen-containing material.
Yoo discloses depositing a dielectric or insulating layer such as silicon oxide; wherein the substrate is exposed to a silicon precursor; purging the reaction chamber ; exposing the substrate to activate oxygen species; purging the reaction chamber and repeating the steps until the desired initial thickness is reached (Paragraph [0043]). Austin discloses a semiconductor processing method comprising: providing a silicon-containing precursor to a processing region of a semiconductor processing chamber (702), wherein a substrate is housed in the processing region, wherein the substrate defines a feature, and wherein the processing region is at least partially defined between a faceplate (706) and a substrate support (708) on which the substrate (712) is seated (Figure 7 Paragraphs [0066]-[0073]); forming plasma effluents of the silicon-containing precursor; depositing a silicon-containing material on the substrate; providing an oxygen-containing precursor to the processing region of the semiconductor processing chamber; forming plasma effluents of the oxygen-containing precursor; contacting the silicon-containing material with the plasma effluents of the oxygen-containing precursor to oxidize the silicon-containing material, wherein the contacting forms a silicon-and-oxygen-containing material (Paragraphs [0037]-[0061] discloses forming a dielectric layer 212 to fill the gap by introducing a silicon containing precursor; exposing the dielectric layer to an oxidizing plasma wherein the gap is particularly filled with silicon oxide and the steps can be repeated). As such Yoo as modified Austin renders obvious wherein the processing region is at least partially defined between a faceplate and a substrate support on which the substrate is seated; forming plasma effluents of the silicon-containing precursor; depositing a silicon-containing material on the substrate; providing an oxygen-containing precursor to the processing region of the semiconductor processing chamber; forming plasma effluents of the oxygen-containing precursor; contacting the silicon-containing material with the plasma effluents of the oxygen-containing precursor to oxidize the silicon-containing material, wherein the contacting forms a silicon-and-oxygen-containing material.
It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the invention to modify the method of Yoo to include the deposition and oxidizing as rendered obvious by Austin because the reference of Austin teach method provides for a silicon oxide film to partially fill a gap (Paragraph [0061]) and one of ordinary skill in the art prior to the effective filing date of the invention would have had a reasonable expectation of predictably achieving the desired plasma processing using the processing chamber, depositing and oxidizing as rendered obvious by Austin. MPEP 2143D
With regards to claim 19, Yoo discloses a semiconductor processing method comprising: providing a silicon-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is housed in the processing region, wherein the substrate defines a feature, forming plasma effluents of the silicon-containing precursor; providing an oxygen-containing precursor to the processing region of the semiconductor processing chamber; forming plasma effluents of the oxygen-containing precursor; forming a silicon and oxygen containing material (silicon oxide) wherein the contacting forms a silicon-and-oxygen-containing material; providing a fluorine-containing precursor to the processing region of the semiconductor processing chamber; forming plasma effluents of the fluorine-containing precursor; and contacting the silicon-and-oxygen-containing material (silicon oxide) with plasma effluents of the fluorine-containing precursor, wherein the contacting etches the silicon-and-oxygen-containing material from a top, a sidewall, or both of the feature. (Paragraphs [0039]-[0048], [0053], Figures 3-4 discloses removing material 41 from the top and sidewall).
Yoo does not explicitly disclose wherein the processing region is at least partially defined between a faceplate and a substrate support on which the substrate is seated; forming plasma effluents of the silicon-containing precursor, wherein the plasma effluents of the silicon-containing precursor are formed at a first power level from a plasma power source; depositing a silicon-containing material on the substrate; providing an oxygen-containing precursor to the processing region of the semiconductor processing chamber; forming plasma effluents of the oxygen-containing precursor; contacting the silicon-containing material with the plasma effluents of the oxygen-containing precursor to oxidize the silicon-containing material, wherein the contacting forms a silicon-and-oxygen-containing material;
Yoo discloses depositing a dielectric or insulating layer such as silicon oxide; wherein the substrate is exposed to a silicon precursor; purging the reaction chamber ; exposing the substrate to activate oxygen species; purging the reaction chamber and repeating the steps until the desired initial thickness is reached (Paragraph [0043]) wherein the plasma effluents of the silicon containing precursor are formed at a fist power level from a plasma power source in the range of about 400 W to about 1500W (Yoo Paragraph [0044]) and the plasma effluents of the fluorine-containing precursor are formed at a second power level from about 100 W to about 600W (Yoo Paragraph [0048]) rendering obvious where the second power source greater than the first power level (Yoo Paragraphs [0044], [0048] discloses wherein the first power level may be as low as 400W while the second power level is as high as 600 W rendering obvious Applicant’s claimed range). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). MPEP 2144.05(I)
It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the invention to modify the method of Yoo to include the plasma power as rendered obvious by general teachings of Yoo because one of ordinary skill in the art prior to the effective filing date of the invention would have had a reasonable expectation of predictably achieving the desired plasma processing using the plasma power as rendered obvious by Yoo. MPEP 2143D
Austin discloses a semiconductor processing method comprising: providing a silicon-containing precursor to a processing region of a semiconductor processing chamber (702), wherein a substrate is housed in the processing region, wherein the substrate defines a feature, and wherein the processing region is at least partially defined between a faceplate (706) and a substrate support (708) on which the substrate (712) is seated (Figure 7 Paragraphs [0066]-[0073]); forming plasma effluents of the silicon-containing precursor; depositing a silicon-containing material on the substrate; providing an oxygen-containing precursor to the processing region of the semiconductor processing chamber; forming plasma effluents of the oxygen-containing precursor; contacting the silicon-containing material with the plasma effluents of the oxygen-containing precursor to oxidize the silicon-containing material, wherein the contacting forms a silicon-and-oxygen-containing material (Paragraphs [0037]-[0061] discloses forming a dielectric layer 212 to fill the gap by introducing a silicon containing precursor; exposing the dielectric layer to an oxidizing plasma wherein the gap is particularly filled with silicon oxide and the steps can be repeated). As such Yoo as modified Austin renders obvious wherein the processing region is at least partially defined between a faceplate and a substrate support on which the substrate is seated; forming plasma effluents of the silicon-containing precursor; depositing a silicon-containing material on the substrate; providing an oxygen-containing precursor to the processing region of the semiconductor processing chamber; forming plasma effluents of the oxygen-containing precursor; contacting the silicon-containing material with the plasma effluents of the oxygen-containing precursor to oxidize the silicon-containing material, wherein the contacting forms a silicon-and-oxygen-containing material.
It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the invention to modify the method of Yoo to include the deposition and oxidizing as rendered obvious by Austin because the reference of Austin teach method provides for a silicon oxide film to partially fill a gap (Paragraph [0061]) and one of ordinary skill in the art prior to the effective filing date of the invention would have had a reasonable expectation of predictably achieving the desired plasma processing using the processing chamber, depositing and oxidizing as rendered obvious by Austin. MPEP 2143D
With regards to claim 2, the modified teachings of Yoo renders obvious wherein: the feature is characterized by an aspect ratio of greater than or about 1:1; and the feature is characterized by a width across the feature of less than or about 100 nm. (Yoo Paragraph [0040], Austin Paragraph [0027]).
With regards to claim 3, the modified teachings of Yoo renders obvious wherein the oxygen-containing precursor comprises diatomic oxygen (O2) or nitrous oxide (N2O). (Yoo Paragraph [0043], Austin Paragraph [0061]).
With regards to claim 6, the modified teachings of Yoo discloses wherein the plasma effluents of the silicon containing precursor are formed at a fist power level from a plasma power source in the range of about 400 W to about 1500W (Yoo Paragraph [0044]) and the plasma effluents of the fluorine-containing precursor are formed at a second power level from about 100 W to about 600W (Yoo Paragraph [0048]) rendering obvious where the second power source greater than the first power level (Yoo Paragraphs [0044], [0048] discloses wherein the first power level may be as low as 400W while the second power level is as high as 600 W rendering obvious Applicant’s claimed range). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). MPEP 2144.05(I)
With regards to claim 7, the modified teachings of Yoo renders obvious wherein the fluorine-containing precursor comprises diatomic fluorine (F2), nitrogen trifluoride (NF3), ammonia (NH3), octafluorocyclobutane (C4F8), carbon tetrafluoride (CF4), or hexafluorobutadiene (C4F6). (Yoo Paragraph [0047]).
With regards to claim 8, the modified teaching of Yoo discloses wherein the etching removes the silicon-and-oxygen containing material wherein the thickness of material 412 at the top of the feature is removed (Paragraph [0041], [0045]) wherein the activated species are provided t5 at a flowrate of etchant in the range of 1000 sccm to about 500 sccm for etching the thickness of material (Paragraph [0057]) Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) MPEP 2144.05(II)(A) Therefore it would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the invention to optimize the removal etch rate to amounts including applicant’s claimed amount of an etch rate of less than or about 10 Å/second in order to sufficiently remove the thickness of material in the time period and etchant flow rate as taught by the modified teachings of Yoo (Yoo Paragraphs [0041], [0045], [0051] MPEP 2144.05(II)(A)).
With regards to claim 9, the modified teachings of Yoo renders obvious wherein the method is repeated for a second cycle (Yoo Paragraph [0050] repeated multiple times until the desired thickness is reached).
With regards to clams 10, 18 and 20, the modified teachings of Yoo renders obvious wherein a temperature of the substrate is maintained at a temperature of less than or about 450 °C. (Paragraph [0044]).
With regards to claim 11, the modified teachings of Yoo renders obvious wherein a pressure within the semiconductor processing chamber is maintained at a pressure of less than or about 10 Torr. (Yoo Paragraph [0044])
With regards to claim 13, the modified teachings of Yoo discloses wherein a plasma power during operation iii) is maintained in the range of about 400 W to about 1500W (Yoo Paragraph [0044]) which renders obvious iii) is maintained at greater than or about 600 W. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). MPEP 2144.05(I)
Claims 4-5 and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over YOO et al (U.S. Patent Application Publication 2021/0035854) in view of AUSTIN et al (WO 2021/202808), as applied to claims 1-3, 6-13 and 18-20, in further view of JIANG et al (U.S. Patent Application Publication 2022/0020594).
With regards to claims 4-5, the modified teachings of Yoo renders obvious the limitations of claim 1 as previously discussed.
However the modified teachings of Yoo are silent as to applying a bias power from a bias power source to the substrate support and wherein a plasma power source is operated in a continuous wave mode while the bias power source is operated in a pulsing mode during the depositing and the etching.
Jiang discloses a semiconductor processing method comprising forming a silicon containing material and etching the silicon containing material with a plasma to form a gap fill wherein the method comprises applying a bias power from a bias power source to the substrate support and wherein a plasma power source is operated in a continuous wave mode while the bias power source is operated in a pulsing mode during the depositing and the etching (Paragraphs [0026], [0035]-[0042] discloses applying a bias power from a bias power source which maybe pulsed in a duty cycle).
It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the invention to further modify the modified method of Yoo to include the bias power as rendered obvious by Jiang because the reference of Jiang teaches that the bias power can be adjust to etch the deposit materials along the sidewall (Paragraph [0042]) and one of ordinary skill in the art prior to the effective filing date of the invention would have had a reasonable expectation of predictably achieving the desired substrate processing using the bias power as rendered obvious by Jiang. MPEP 2143D
With regards to claims 14-17, the modified teachings Yoo renders obvious the limitation of claim 12 as previously discussed.
However the modified teachings of Yoo are silent as to wherein a plasma power is pulsed during operations i) through iv); wherein the etching fully removes the silicon-and-oxygen-containing material from sidewalls of the feature above a base fill of the feature; applying a bias power from a bias power source during the semiconductor processing method and wherein the bias power source is operated at a plasma power of less than or about 750 W.
Jiang discloses a semiconductor processing method comprising forming a silicon containing material and etching the silicon containing material with a plasma to form a gap fill wherein the method comprising providing a plasma power wherein the plasma power during deposition or etching may be pulsed (Paragraphs [0036]-[0037], [0039]-[0042]); wherein the etching is performed to remove the sidewalls and overhang region of the deposited material (Figure 3B Paragraph [0041]); and wherein a bias power may be applied wherein the bias power is below or about 500W (Paragraph [0039]) rendering obvious wherein a plasma power is pulsed during operations i) through iv); wherein the etching fully removes the silicon-and-oxygen-containing material from sidewalls of the feature above a base fill of the feature; applying a bias power from a bias power source during the semiconductor processing method and wherein the bias power source is operated at a plasma power of less than or about 750 W. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). MPEP 2144.05(I)
It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the invention to further modify the modified method of Yoo to include the pulsing power and bias power as rendered obvious by Jiang because the reference of Jiang teaches that the plasma power or bias power can be adjust to etch the deposit materials along the sidewall (Paragraph [0042]) and one of ordinary skill in the art prior to the effective filing date of the invention would have had a reasonable expectation of predictably achieving the desired substrate processing using the plasma power and bias power as rendered obvious by Jiang. MPEP 2143D
Conclusion
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/STEPHANIE P DUCLAIR/Primary Examiner, Art Unit 1713