DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Entry of Amendments
Claim(s) 1, 6, 8, 10 and 15 have been amended.
Rejections under 35 USC 102 and 103
Applicant’s amendments filed 01/08/2026 with respect to Claim(s) 1-5 and 8-16 have been fully considered but they are not persuasive.
Applicant's arguments with respect to Claim(s) 1-16 have been considered but are moot because the arguments do not apply to the reference(s) and/or ground(s) being used in the current rejection.
For further details see the rejections/objections for Claim(s) 1-16 herein.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4, 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Tajima et al. (US 20120077408; hereinafter Tajima) in view of LUO et al (US 20250185365).
Regarding claim 1, Tajima teaches in figure(s) 1-15 An element test device comprising
a display panel (para. 64 - a display panel including a plurality of pixels arranged in a matrix) on which electrical elements comprising thin-film transistors and light emitting elements (para. 142 - liquid crystal layer 40) are located (paras. 10-11 :- active matrix substrate 120 includes a plurality of pixel electrodes 118 arranged in a matrix … TFT 105 includes a semiconductor layer 112 provided on the substrate; fig. 9);
a test panel (19; para. 64 - a stage configured to place a test panel which will become the display panel) that extends from the display panel or is integral with the display panel, and on which test electrical elements comprising other thin-film transistors (para. 90 - an array testing device 41a for accessing TFTs in the pixels of the test substrate 19 to write charge to the auxiliary capacitors of the pixels) are located; and
a test signal processor (para. 90 - defective pixel detector 40a includes a prober 42 for inputting a test signal to the test substrate 19, an array testing device 41a for accessing TFTs in the pixels of the test substrate 19 to write charge to the auxiliary capacitors of the pixels; fig. 1) configured to substantially simultaneously supply a first driving voltage and a second driving voltage to the test electrical elements (para. 125,17 - the signal (source) line number and scanning (gate line) number of a defective pixel having a short-circuit defect S are determined, whereby the coordinates of the defective pixel in the test substrate 19 are found) using a first channel and a second channel, respectively, and to detect electrical output characteristics of the test electrical elements using a number of k channels equal to a number of the test electrical elements (para. 47 - a scanning test signal input to the gate line is set apart from the angular velocity .omega. of an alternating- current voltage applied to promote heat generation; fig. 13).
Tajima does not teach explicitly the test electrical elements being formed through a same manufacturing process as the electrical elements.
However, LUO teaches in figure(s) 1-4 The test electrical elements (pressure-sensitive transistor area of backpanel 11; fig. 1) being formed through a same manufacturing process (para. 36 - the first conductive layer 81, the second conductive layer 82, and the third conductive layer 83 are located in a same layer in the TFT back panel 110 and can be formed in the same manufacturing process) as the electrical elements (display transistor area; LED bonding area).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Tajima by having the test electrical elements being formed through a same manufacturing process as the electrical elements as taught by LUO in order to provide use of known technique to improve similar devices (methods, or products) in the same way as evidenced by "pressure-sensitive transistor is thus turned on to generate a current, and a pressure signal is converted into an electrical signal, thereby monitoring changes in the pressure applied to the TFT back panel 110 during the ACF pressing process in real time" (para. 22).
Regarding claim 2, Tajima teaches in figure(s) 1-15 the element test device of claim 1, further comprising:
a loader (stage 30a with stage controller 31; abs. - a stage (30a) configured to place a test substrate (19) which will become the active matrix substrate) for receiving the display panel and the test panel;
a power supply (power supply 67) configured to generate the first driving voltage and the second driving voltage to be supplied to the test electrical elements (para. 142 - alignment state of the liquid crystal layer is changed by changing the magnitude of the voltage applied to the liquid crystal layer 40 to adjust the light transmittance of the liquid crystal layer); and
a contact terminal unit (para. 18 - a plurality of separated capacitor electrodes for each of the pixels, where the plurality of separated capacitor electrodes for each of the pixels overlap the corresponding capacitor line with an insulating film being interposed therebetween and are connected to the corresponding thin film transistor) comprising contact terminals respectively contacting first electrodes, second electrodes, and third electrodes of the test electrical elements.
Regarding claim 4, Tajima teaches in figure(s) 1-15 the element test device of claim 2, wherein the contact terminals comprise: first electrode contact terminals respectively contacting the first electrodes (14) of the test electrical elements; second electrode contact terminals respectively contacting the second electrodes (16) of the test electrical elements; and third electrode contact terminals respectively contacting the third electrodes (12,18) of the test electrical elements.
Regarding claim 10, Tajima teaches in figure(s) 1-15 An element test device comprising:
a display panel (para. 64 - a display panel including a plurality of pixels arranged in a matrix) on which electrical elements comprising thin-film transistors and light emitting elements (para. 142 - liquid crystal layer 40) are located (paras. 10-11 :- active matrix substrate 120 includes a plurality of pixel electrodes 118 arranged in a matrix … TFT 105 includes a semiconductor layer 112 provided on the substrate; fig. 9);
a test panel (19; para. 64 - a stage configured to place a test panel which will become the display panel) that extends from the display panel or is integral with the display panel, and on which test electrical elements comprising other thin-film transistors (para. 90 - an array testing device 41a for accessing TFTs in the pixels of the test substrate 19 to write charge to the auxiliary capacitors of the pixels);
a loader (stage 30a with stage controller 31; abs. - a stage (30a) configured to place a test substrate (19) which will become the active matrix substrate) configured to receive the display panel and the test panel;
a power supply (power supply 67) configured to generate a first driving voltage and a second driving voltage to be supplied to the test electrical elements (para. 142 - alignment state of the liquid crystal layer is changed by changing the magnitude of the voltage applied to the liquid crystal layer 40 to adjust the light transmittance of the liquid crystal layer);
a contact terminal unit (para. 18 - a plurality of separated capacitor electrodes for each of the pixels, where the plurality of separated capacitor electrodes for each of the pixels overlap the corresponding capacitor line with an insulating film being interposed therebetween and are connected to the corresponding thin film transistor) comprising contact terminals respectively contacting first electrodes (14), second electrodes (16), and third electrodes (12,18) of the test electrical elements; and
a test signal processor (para. 90 - defective pixel detector 40a includes a prober 42 for inputting a test signal to the test substrate 19, an array testing device 41a for accessing TFTs in the pixels of the test substrate 19 to write charge to the auxiliary capacitors of the pixels; fig. 1) configured to substantially simultaneously supply the first driving voltage and the second driving voltage to the test electrical elements (para. 125,17 - the signal (source) line number and scanning (gate line) number of a defective pixel having a short-circuit defect S are determined, whereby the coordinates of the defective pixel in the test substrate 19 are found) using a first channel and a second channel, respectively, and to detect electrical output characteristics of the test electrical elements using a number of k channels equal to the number of the test electrical elements (para. 47 - a scanning test signal input to the gate line is set apart from the angular velocity .omega. of an alternating- current voltage applied to promote heat generation; fig. 13).
Tajima does not teach explicitly the test electrical elements being formed through a same manufacturing process as the electrical elements.
However, LUO teaches in figure(s) 1-4 The test electrical elements (pressure-sensitive transistor area of backpanel 11; fig. 1) being formed through a same manufacturing process (para. 36 - the first conductive layer 81, the second conductive layer 82, and the third conductive layer 83 are located in a same layer in the TFT back panel 110 and can be formed in the same manufacturing process) as the electrical elements (display transistor area; LED bonding area).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Tajima by having the test electrical elements being formed through a same manufacturing process as the electrical elements as taught by LUO in order to provide use of known technique to improve similar devices (methods, or products) in the same way as evidenced by "pressure-sensitive transistor is thus turned on to generate a current, and a pressure signal is converted into an electrical signal, thereby monitoring changes in the pressure applied to the TFT back panel 110 during the ACF pressing process in real time" (para. 22).
Regarding claim 12, Tajima teaches in figure(s) 1-15 the element test device of claim 10, wherein the contact terminals comprise: first electrode contact terminals respectively contacting the first electrodes (14) of the test electrical elements; second electrode contact terminals respectively contacting the second electrodes (16) of the test electrical elements; and third electrode contact terminals respectively contacting the third electrodes (12,18) of the test electrical elements.
Claim(s) 3, 5, 8-9, 11, 13 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Tajima in view of LUO, and further in view of Jo et al. (US 20040108518).
Regarding claim 3, Tajima teaches in figure(s) 1-15 the element test device of claim 2,
Tajima does not teach explicitly wherein the test signal processor is configured to substantially simultaneously supply the first driving voltage to the first electrodes of the test electrical elements through a first channel line of the contact terminal unit, to substantially simultaneously supply the second driving voltage to the second electrodes of the test electrical elements through a second channel line of the contact terminal unit, and to detect electrical characteristics comprising voltages and current amounts of electrical signals respectively output from the third electrodes of the test electrical elements through k channel lines and the k channels of the contact terminal unit.
However, Jo teaches in figure(s) 1-9 wherein the test signal processor is configured to substantially simultaneously supply the first driving voltage (Va; fig. 3) to the first electrodes of the test electrical elements through a first channel line of the contact terminal unit, to substantially simultaneously supply the second driving voltage (Vb) to the second electrodes of the test electrical elements through a second channel line of the contact terminal unit, and to detect electrical characteristics comprising voltages and current amounts (12a,19a) of electrical signals respectively output from the third electrodes of the test electrical elements through k channel lines (16a/19a/X1, 16a/19a/Xn) and the k channels of the contact terminal unit.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Tajima by having wherein the test signal processor is configured to substantially simultaneously supply the first driving voltage to the first electrodes of the test electrical elements through a first channel line of the contact terminal unit, to substantially simultaneously supply the second driving voltage to the second electrodes of the test electrical elements through a second channel line of the contact terminal unit, and to detect electrical characteristics comprising voltages and current amounts of electrical signals respectively output from the third electrodes of the test electrical elements through k channel lines and the k channels of the contact terminal unit as taught by Jo in order to provide applying a known technique to a known device (method, or product) ready for improvement to yield predictable results as evidenced by "method of driving the electronic circuit, electrooptical device, and electronic equipment for detecting operational characteristics of the electronic circuit at a high precision" (abstract).
Regarding claim 8, Tajima teaches in figure(s) 1-15 the element test device of claim 2,
Tajima does not teach explicitly Tajima does not teach explicitly wherein the contact terminals comprise: four first electrode contact terminals respectively contacting first electrodes of first through fourth thin-film transistors among the test electrical elements; four second electrode contact terminals respectively contacting second electrodes of the first through fourth thin-film transistors; and four third electrode contact terminals respectively contacting third electrodes of the first through fourth thin-film transistors.
However, Jo teaches in figure(s) 1-9 wherein the contact terminals comprise: four first electrode contact terminals respectively contacting first electrodes (Va/20 @ X1…X4) of first through fourth thin-film transistors among the test electrical elements; four second electrode contact terminals respectively contacting second electrodes (Vb/20 @ X1…X4) of the first through fourth thin-film transistors; and four third electrode contact terminals respectively contacting third electrodes of the first through fourth thin-film transistors (Xm @ X1…X4; fig. 3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Tajima by having wherein the contact terminals comprise: four first electrode contact terminals respectively contacting first electrodes of first through fourth thin-film transistors among the test electrical elements; four second electrode contact terminals respectively contacting second electrodes of the first through fourth thin-film transistors; and four third electrode contact terminals respectively contacting third electrodes of the first through fourth thin-film transistors as taught by Jo in order to provide "data line can be used as a test line without arranging a dedicated test line." (para. 29).
Regarding claim 5 and 9, Tajima teaches in figure(s) 1-15 the element test device of claim 4 and 8, respectively.
Tajima does not teach explicitly wherein the contact terminal unit further comprises:
a first channel line connecting the first electrode contact terminals to one first channel in a parallel structure;
a second channel line connecting the second electrode contact terminals to one second channel in a parallel structure; and
k channel lines connecting the third electrode contact terminals to the k channels in a one-to-one manner.
However, Jo teaches in figure(s) 1-9 wherein the contact terminal unit further comprises:
a first channel line (SL1) connecting the first electrode contact terminals to one first channel in a parallel structure;
a second channel line (SL2) connecting the second electrode contact terminals to one second channel in a parallel structure; and
k channel lines (16a/19a/X1, 16a/19a/Xn) connecting the third electrode contact terminals to the k channels in a one-to-one manner.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Tajima by having wherein the contact terminal unit further comprises: a first channel line connecting the first electrode contact terminals to one first channel in a parallel structure; a second channel line connecting the second electrode contact terminals to one second channel in a parallel structure; and k channel lines connecting the third electrode contact terminals to the k channels in a one-to-one manner as taught by Jo in order to provide "electrooptical device employing the organic EL element uses an active-matrix addressing method as one of driving methods." (para. 4).
Regarding claim 11, Tajima teaches in figure(s) 1-15 the element test device of claim 10,
Tajima does not teach explicitly wherein the test signal processor is configured to substantially simultaneously supply the first driving voltage to the first electrodes of the test electrical elements through a first channel line of the contact terminal unit, to substantially simultaneously supply the second driving voltage to the second electrodes of the test electrical elements through a second channel line of the contact terminal unit, and to detect electrical characteristics comprising voltages and current amounts of electrical signals respectively output from the third electrodes of the test electrical elements through k channel lines and the k channels of the contact terminal unit.
However, Jo teaches in figure(s) 1-9 wherein the test signal processor is configured to substantially simultaneously supply the first driving voltage (Va; fig. 3) to the first electrodes of the test electrical elements through a first channel line of the contact terminal unit, to substantially simultaneously supply the second driving voltage (Vb) to the second electrodes of the test electrical elements through a second channel line of the contact terminal unit, and to detect electrical characteristics comprising voltages and current amounts (12a,19a) of electrical signals respectively output from the third electrodes of the test electrical elements through k channel lines (16a/19a/X1, 16a/19a/Xn) and the k channels of the contact terminal unit.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Tajima by having wherein the test signal processor is configured to substantially simultaneously supply the first driving voltage to the first electrodes of the test electrical elements through a first channel line of the contact terminal unit, to substantially simultaneously supply the second driving voltage to the second electrodes of the test electrical elements through a second channel line of the contact terminal unit, and to detect electrical characteristics comprising voltages and current amounts of electrical signals respectively output from the third electrodes of the test electrical elements through k channel lines and the k channels of the contact terminal unit as taught by Jo in order to provide "method of driving the electronic circuit, electrooptical device, and electronic equipment for detecting operational characteristics of the electronic circuit at a high precision" (abstract).
Regarding claim 15, Tajima teaches in figure(s) 1-15 the element test device of claim 10,
Tajima does not teach explicitly wherein the contact terminals comprise: four first electrode contact terminals respectively contacting first electrodes of first through fourth thin-film transistors among the test electrical elements; four second electrode contact terminals respectively contacting second electrodes of the first through fourth thin-film transistors; and four third electrode contact terminals respectively contacting third electrodes of the first through fourth thin-film transistors.
However, Jo teaches in figure(s) 1-9 wherein the contact terminals comprise: four first electrode contact terminals respectively contacting first electrodes (Va/20 @ X1…X4) of first through fourth thin-film transistors among the test electrical elements; four second electrode contact terminals respectively contacting second electrodes (Vb/20 @ X1…X4) of the first through fourth thin-film transistors; and four third electrode contact terminals respectively contacting third electrodes of the first through fourth thin-film transistors (Xm @ X1…X4; fig. 3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Tajima by having wherein the contact terminals comprise: four first electrode contact terminals respectively contacting first electrodes of first through fourth thin-film transistors among the test electrical elements; four second electrode contact terminals respectively contacting second electrodes of the first through fourth thin-film transistors; and four third electrode contact terminals respectively contacting third electrodes of the first through fourth thin-film transistors as taught by Jo in order to provide "data line can be used as a test line without arranging a dedicated test line." (para. 29).
Regarding claim 13 and 16, Tajima teaches in figure(s) 1-15 the element test device of claim 12 and 15, respectively.
Tajima does not teach explicitly wherein the contact terminal unit further comprises: a first channel line connecting the first electrode contact terminals to one first channel in a parallel structure; a second channel line connecting the second electrode contact terminals to one second channel in a parallel structure; and k channel lines connecting the third electrode contact terminals to the k channels in a one-to-one manner.
However, Jo teaches in figure(s) 1-9 wherein the contact terminal unit further comprises: a first channel line (SL1) connecting the four first electrode contact terminals to one first channel in a parallel structure; a second channel line (SL2) connecting the four second electrode contact terminals to one second channel in a parallel structure; and k channel lines (16a/19a/X1, 16a/19a/Xn) connecting the four third electrode contact terminals to the k channels in a one-to-one manner.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Tajima by having wherein the contact terminal unit further comprises: a first channel line connecting the first electrode contact terminals to one first channel in a parallel structure; a second channel line connecting the second electrode contact terminals to one second channel in a parallel structure; and k channel lines connecting the third electrode contact terminals to the k channels in a one-to-one manner as taught by Jo in order to provide "electrooptical device employing the organic EL element uses an active-matrix addressing method as one of driving methods." (para. 4).
Allowable Subject Matter
Claim(s) 6-7 are allowed.
Claim(s) 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim(s) 6 and 14, the prior arts of record do not fairly teach or suggest “wherein the test signal processor, during a first period, is configured to supply the first driving voltage having a first voltage level to the first channel line, to supply the second driving voltage having a gradually varying voltage level to the second channel line, and to detect electrical signals respectively output from the third electrodes of the test electrical elements through the k channel lines, and, during a second period, is configured to supply the first driving voltage having a second voltage level that is different from the first voltage level to the first channel line, to supply the second driving voltage having a gradually varying voltage level to the second channel line, and to detect electrical signals respectively output from the third electrodes of the test electrical elements through the k channel lines.” including all of the limitations of the base claim and any intervening claims.
Claim(s) 7 are allowed for dependent upon base claim 6.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKM ZAKARIA whose telephone number is (571)270-0664. The examiner can normally be reached on 8-5 PM (PST).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JUDY NGUYEN can be reached on 571-272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AKM ZAKARIA/
Primary Examiner, Art Unit 2858
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