Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
In response to the requirement for restriction/election filed on 05/31/2026, the applicant elects invention I, claims 1-17, without traverse. Additionally, applicant adds claims 21-23, which do not contain new matter. Thus, claim 1-17, and 21-23 are examined upon the merits below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10-15, and 21-22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fan et al (US 20180350743).
[claim 10] A method of fabricating a semiconductor device, comprising: forming a source region and a drain region in a substrate (figures 10 and 11, paragraph 0022, where elements 204a/b/c are the source and drain regions formed in a substrate [element 102]),
forming a gate structure on the substrate, wherein the gate structure extends in a first direction and has a length in a second direction different from the first direction (figures 11 and 12, paragraph 0023, where element 106 is the gate structure comprised of a plurality of discrete gates, elements 106a and 106b, where the first direction is the vertical direction and the gate extends in said direction, and the second direction [different than the first] is the horizontal direction),
the source region and the drain region are disposed on opposite sides of the gate structure, and a distance between the source region and the drain region in the second direction is greater than the length of the gate structure (figures 10-12, paragraphs 0022 and 0023, where element 204a/b/c are all separated by a distance that is greater than the width of the discrete gate structures in the second direction [horizontal direction]),
depositing an ILD layer to cover the substrate and the gate structure (figure 14, paragraph 0057, where element 1402 is the ILD layer over the gate structures [elements 106a/b] and over the substrate [element 102]);
forming a first conductive contact penetrating the ILD layer and connected to the gate structure (figure 14, paragraph 0057, where element 110 over element 106a is the first conductive contact penetrating the ILD layer [element 1402] and connected to the gate structure [specifically the portion of element 106a]);
and forming a plurality of conductive plates penetrating the ILD layer and connected to the gate structure, wherein each conductive plate overlaps an area between the gate structure and one of the source and drain regions (figures 14 and 16B, paragraph 0057, where the plurality of conductive plates is seen in figure 16B by element 110 on the top side and bottom side, which corresponds to element 110 of figure 14, which is placed over the gate structure [specifically the portion 106b] and overlaps an area between the gate structure and the source and drain regions [between element 106b and 204b/c]).
[claim 11] The method of claim 10, wherein the first conductive contact and the conductive plates are simultaneously formed (figure 14, paragraph 0057, where element 110 is formed in the same step, thus element 110 over element 106a and elements 110 over element 106b are all formed at the same time).
[claim 12] The method of claim 10, wherein the conductive plates are symmetric about a central axis of the gate structure, and the central axis is parallel to the first direction (figure 14, paragraph 0057, where element 110 over element 106b [and according to figure 16B, both elements 110 over element 106b are symmetrical], where the conductive plate is symmetrical about a central axis of the gate structure, 106b, which extends in the vertical direction and is parallel to the first direction [vertical direction]).
[claim 13] The method of claim 10, wherein the plurality of conductive plates extend toward one of the source region and the drain region and are evenly spaced in the first direction (figure 14, paragraph 0057, where element 110 extends towards the gate and source structures [element 204b/c], thus extends towards at least one of the two, and evenly spaced in the vertical direction [first direction]).
[claim 14] The method of claim 10, further comprising forming a plurality of second conductive contacts penetrating the ILD layer and connected to the source region and the drain region (figure 14, paragraph 0057, where element 108a/b/c are the source contacts formed in the ILD layer and connected to the source and drain regions 204a/b/c).
[claim 15] The method of claim 14, further comprising forming a first interconnect structure and a second interconnect structure over the ILD layer, the first conductive contact, the second conductive contacts, and the conductive plates (figure 15, paragraphs 0059-0060, where elements 112b-c comprise the first interconnect structure [element 112b] and the second interconnect structure [element 112c-d] situated over the ILD layer [element 1402], conductive contacts [element 110 over element 106a] and conductive plates [element 110 over element 106b]),
wherein the first interconnect structure is physically connected to the first conductive contact, and the second interconnect structure is physically connected to the second conductive contacts (figure 15, paragraphs 0059-0060, where element 112b [first interconnect structure] is connected to the conductive contact [element 110 over element 106a] and elements 112c-d [second interconnect structure] is connected to the conductive plates [elements 110 over element 106b]).
[claim 21] A method of fabricating a semiconductor device, comprising: forming a source region and a drain region in a substrate (figures 10 and 11, paragraph 0022, where elements 204a/b/c are the source and drain regions formed in a substrate [element 102]);
forming a gate electrode over the substrate (figures 11 and 12, paragraph 0023, where element 106 is the gate structure comprised of a plurality of discrete gates, elements 106a and 106b);
depositing an inter-layer dielectric (ILD) layer over the gate electrode (figure 14, paragraph 0057, where element 1402 is the ILD layer formed over the gate electrode [elements 106a/b]);
forming a first trench and a plurality of second trenches through the ILD layer, wherein the first trench is disposed outside an active area and exposes a first portion of the gate electrode, and each second trench of the plurality of second trenches is disposed inside the active area, exposes a second portion of the gate electrode, and, from a top-view perspective, overlaps an area between the gate electrode and one of the source region and the drain region (figures 14 and 16B, paragraphs 0057-0060, where element 110 over element 106a is the area where the first trench is formed, and element 110 over element 106b is the second trench where according to figure 16B a plurality of second trenches must be formed to form both element 110 on the top of the page and on the bottom of the page. The first trench is formed over a gate electrode [element 106a] and the second trenches are formed over the gate [element 106b] and between the source/drain regions as well [elements 204a-c]. According to paragraph 0057, etching takes place before filling in the material of 110 into the ILD, thus a trench is formed through etching in the same location that element 110 is present in the ILD in figure 14);
and depositing a first conductive material in the first trench and the plurality of second trenches to respectively form a first conductive contact and a plurality of conductive plates electrically connected to the gate electrode (figures 14 and 16B, paragraphs 0057-0060, where element 110 over element 106a is the first conductive contact filled in the first trench, and element 110 over element 106b is the plurality of conductive plates electrically connected to the gate electrode [element 106b] situated in the second trench where according to figure 16B a plurality of second trenches must be formed to form both element 110 on the top of the page and on the bottom of the page).
[claim 22] The method of Claim 21, wherein the forming of the first trench and the plurality of second trenches comprises simultaneously etching the ILD layer in at least one etching operation (figures 14 and 16B, paragraph 0057, where element 110 [where the first and second trenches are formed] is etched to be a trench simultaneously, where a conductive material is filled into said trenches after etching).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, and 8-9, is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al (US 20220052168) in view of Chou et al (US 20170148911).
Fan et al teaches
[claim 1] A method of fabricating a semiconductor device, comprising: forming a source region and a drain region (figures 1 and 2, paragraph 0017, where element 205-1 is a source and drain region formed),
forming a gate structure on the substrate, wherein the source region and the drain region are disposed on opposite sides of the gate structure and separated from the gate structure by a distance (figures 1 and 2, paragraph 0014, where element 206 is the gate structure where the source and drain [element 205-1] are formed on a side of the gate structure separated by a specific distance [distance is shown to be less than the measurement of W2-W1 as shown in figure 18]),
depositing an inter-layer dielectric (ILD) layer over the substrate and the gate structure (figure 2, paragraph 0014, where element 213 is the ILD formed over the substrate [element 202] and gate structure [element 206])
forming a first trench in the ILD layer, wherein the first trench exposes a first portion of the gate structure and overlies an area between the gate structure and one of the source and drain regions from a top-view perspective (figure 15, paragraphs 0026, where element 242 is the first trench which covers a region over the gate structure [element 206] and between the gate and source/drain [element 205-2])
and depositing a first conductive material in the first trench to form a conductive plate, wherein the conductive plate is electrically connected to the gate structure (figure 16, paragraph 0027, where element 246 is the first conductive material filled in the first trench to form a metal plate which is connected to the gate structure [element 206]).
However, Chang et al does not specifically disclose
[claim 1] [where a source and drain region are formed] in a substrate
However, Chou et al does teach
[claim 1] [where a source and drain region are formed] in a substrate (figure 1, paragraph 0019, where element 104 and 106 is the source/drain region formed in a substrate [element 102]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Chang et al with the teachings of Chou et al to form a source/drain region in a substrate instead of a fin structure to ensure electrical isolation and minimize extra steps for depositing layers [fin layer] thus maximizing efficiency of the materials used for creation of the device.
Additionally, Chang et al as modified does not specifically disclose
[claim 2] The method of claim 1, further comprising: forming a second trench penetrating the ILD layer to expose a second portion of the gate structure, wherein the first trench and the second trench are formed using a same process and depositing the first conductive material in the second trench to form a first conductive contact.
[claim 3] The method of claim 2, further comprising: forming a plurality of first isolation structures in the substrate to define an active region, wherein the first conductive contact is outside the active region, and the conductive plate overlaps the active region from a top-view perspective.
However, Chou et al does disclose
[claim 2] The method of claim 1, further comprising: forming a second trench penetrating the ILD layer to expose a second portion of the gate structure, wherein the first trench and the second trench are formed using a same process and depositing the first conductive material in the second trench to form a first conductive contact (figure 16, paragraph 0088, where the two regions over the gate structure [element 108] are formed by the same process. The first trench is the trench of element 1608, and the second trench is the other trench left of element 1608 formed over the gate structure [element 108] and connects to the gate element which is the first conductive contact – as seen completed in figure 17).
[claim 3] The method of claim 2, further comprising: forming a plurality of first isolation structures in the substrate to define an active region, wherein the first conductive contact is outside the active region, and the conductive plate overlaps the active region from a top-view perspective (figures 7C and 18, paragraph 0054, where element 206 is the plurality of first isolation structures in the substrate to define active regions element 204], where the first conductive contact [element 120 on the left-hand side of element 108] is outside the active region [element 204] and the conductive plate [element 120 over the right-hand side of element 108] overlaps the active region [element 204] from a top-view perspective).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Chang et al as modified to incorporate the teachings of Chou et al to incorporate contacts on the gate structure to allow for connection and control of the gate structure to form a functioning transistor.
Regarding claims 8 and 9, Chang et al further discloses
[claim 8] The method of claim 1, wherein from a top-view perspective, the conductive plate extends from the gate structure toward the source or drain region to overlap an area between the gate structure and the source or drain region (figure 18, paragraph 0027, where element 246 is the conductive plate and it extends over the gate structure [element 206] toward the source/drain region [element 205-2] and a region between).
[claim 9] The method of claim 1, wherein the distance is in a range of about 40 nm to about 50 nm (figure 18, paragraph 0030, where the source/drain region is separated from the gate structure approximately by the distance W2, which is between 40 and 50 nm).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al (US 20220052168), and Chou et al (US 20170148911) and in further view of Pala et al (US 20240055513).
Chang et al as modified teaches all of the limitations of the parent claim, claim 3, but does not specifically disclose
[claim 4] The method of claim 3, further comprising: forming a pair of guard regions in the active region and on opposite sides of the source and drain regions, wherein the guard regions have a first conductivity type and the source and drain regions have a second conductivity type different from the first conductivity type.
However, Pala et al does teach
[claim 4] The method of claim 3, further comprising: forming a pair of guard regions in the active region and on opposite sides of the source and drain regions, wherein the guard regions have a first conductivity type and the source and drain regions have a second conductivity type different from the first conductivity type (figure 1, abstract and paragraph 0048, where the source and drain are formed with first conductivity type, and the guard regions are formed on either side of the source/drain regions of second conductivity type which is different than the first conductivity type).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Chang et al as modified to incorporate the teachings of Pala et al in order to provide guard regions to improve source/drain isolation to prevent any parasitic effects or stray charges floating out of the source/drain thus ensuring better performance of the device.
Claim(s) 5 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al (US 20220052168), and Chou et al (US 20170148911) in further view of Wu et al (US 20220367261).
Chang et al as modified teaches all of the limitations of the parent claim, claim 2, but does not specifically disclose
[claim 5] The method of claim 2, further comprising: forming a plurality of third trenches penetrating the ILD layer to expose the source region and the drain region; depositing a metal layer in the third trenches and onto the source region and the drain region; performing an annealing operation to react the metal layer with the source region and the drain region to form a silicide layer in the third trenches; and depositing a second conductive material in the third trenches over the silicide layer to form a second conductive contact.
However, Wu et al does teach
[claim 5] The method of claim 2, further comprising: forming a plurality of third trenches penetrating the ILD layer to expose the source region and the drain region (figures 20A and 23, paragraph 0050, where elements 94 and 92 are formed first by forming a trench to reach the source/drain region, where metal is then deposited into said trenches);
depositing a metal layer in the third trenches and onto the source region and the drain region; performing an annealing operation to react the metal layer with the source region and the drain region to form a silicide layer in the third trenches; and depositing a second conductive material in the third trenches over the silicide layer to form a second conductive contact (figures 20A and 23, paragraph 0050, where metal is deposited into the trenches to form element 94, an annealing process is performed to form a silicide layer between the contact and the source/drain regions, which is element 92, after silicide layer is formed metal is deposited to form element 94).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Chang et al as modified to incorporate the teachings of Wu et al to form source/drain contacts to connect the source/drain regions to outside circuits to form functioning transistors.
Regarding claim 7,
Chang et al as modified teaches all of the limitations of the parent claim, claim , but does not specifically disclose
[claim 7] The method of claim 5, further comprising: depositing a third dielectric layer on the ILD layer cover the conductive plate; and forming a first interconnect structure in the third dielectric layer, wherein the first interconnect structure is physically and electrically coupled to the first conductive contact.
However, Chou et al further discloses
[claim 7] The method of claim 5, further comprising: depositing a third dielectric layer on the ILD layer cover the conductive plate (figure 1, paragraph 0022, where element 126 is the third ILD layer covering the conductive plate [element 122 of figure 1]);
and forming a first interconnect structure in the third dielectric layer, wherein the first interconnect structure is physically and electrically coupled to the first conductive contact (figure 1, paragraph 0022, where element 128 is the first interconnect structure in the third dielectric layer [element 126] where the first interconnect structure [element 128] is physically and electrically coupled to the first conductive contact [element 122 over the left-hand side of the gate [element 108]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Chang et al as modified to incorporate the teachings of Chou et al to connect the gate structure through the first conductive connector to outside circuitry through an interconnect layer increasing the functionality of the structure.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al (US 20220052168), Chou et al (US 20170148911), Wu et al (US 20220367261) and in further view of Amano et al (US 20210280686).
Change et al as modified teaches all of the limitations of the parent claim, claim 5, but does not specifically disclose
[claim 6] The method of claim 5, further comprising, prior to the formation of the gate structure: forming a first dielectric layer on the substrate; and depositing a second dielectric layer on the first dielectric layer; wherein the third trenches penetrate the first and second dielectric layers, and the first dielectric layer comprises material provided by the substrate.
However, Amano et al does teach
[claim 6] The method of claim 5, further comprising, prior to the formation of the gate structure: forming a first dielectric layer on the substrate; and depositing a second dielectric layer on the first dielectric layer (figures 3 and 5, paragraph 0040, where prior to forming the gate [seen in figure 10 by element 674G], a first and second dielectric layer are formed on the substrate [elements 661, then 662]);
wherein the third trenches penetrate the first and second dielectric layers, and the first dielectric layer comprises material provided by the substrate (figure 5, paragraph 0047, where the third trenches relating to source/drain connections as shown by elements 679S/D, are formed through the first [element 661] and second [element 662] dielectric layers).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Chang et al as modified to incorporate the teachings of Amano et al to use a dielectric layer over the substrate to allow for greater isolation between metallic contacts minimizing any parasitic effects and improving the efficiency of the device.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fan et al (US 20180350743) in view of Wu et al (US 20220367261).
Fan et al teaches all of the limitations of the parent claim, claim 14, but does not specifically disclose
[claim 16] the method of claim 14, further comprising forming a metal silicide layer on the source region and the drain region prior to the formation of the second conductive contacts.
However, Wu et al does teach
[claim 16] the method of claim 14, further comprising forming a metal silicide layer on the source region and the drain region prior to the formation of the second conductive contacts (figures 20A and 23, paragraph 0050, forming a silicide layer [element 92] over the source/drain regions [element 54] prior to forming the second conductive contacts [element 94]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Fan et al as modified to incorporate the teachings of Wu et al to form source/drain contacts to connect the source/drain regions to outside circuits to form functioning transistors.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fan et al (US 20180350743) in view of Chang et al (US 20220052168).
Fan et al teaches all of the limitations of the parent claim, claim 10, but does not specifically disclose
[claim 17] The method of claim 10, wherein a difference between the length of the gate structure and a distance between the source region and the drain region is in a range of about 40 nm to about 50 nm.
However, Chang et al teaches
[claim 17] The method of claim 10, wherein a difference between the length of the gate structure and a distance between the source region and the drain region is in a range of about 40 nm to about 50 nm ((figure 18, paragraph 0030, where the source/drain region is separated from the gate structure approximately by the distance W2, which is between 40 and 50 nm).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Fan et al to incorporate the teachings of Chang et al to have the source/drain regions to be a certain distance from the gate electrode in order to maximize device efficiency and performance by controlling the length of the conducting path between source and drain.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fan et al (US 20180350743) in view of Hou et al (US 20230139258).
Fan et al teaches all of the limitations of the parent claim, claim 21, and further discloses
[claim 23] The method of Claim 21, wherein the depositing of the first conductive material comprises conformally and uniformly depositing the first conductive material on the ILD layer and in the first trench and the plurality of second trenches until the first trench and the plurality of second trenches are filled (figure 14, paragraph 0057, where element 110 [both over element 106a and b] comprises the first conductive material filled in the first and second trenches in the ILD layer [element 1402]),
However, Fan et al does not specifically disclose
[claim 23] and wherein the method further comprises planarizing the first conductive material to remove portions of the first conductive material above an upper surface of the ILD layer.
However, Hou et al does teach
[claim 23] and wherein the method further comprises planarizing the first conductive material to remove portions of the first conductive material above an upper surface of the ILD layer (figure 31B, paragraph 0091, where a planarization process is performed over the source/drain contacts after they fill the first and second trenches above an upper surface of the ILD layer [element 144]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Fan et al to incorporate the teachings of Hou et al to planarize the source/drain contacts to form a smoother edge on top to allow for a smoother top layer to allow for greater spatial efficiency when stacking elements or layers.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yao et al (US 20220359708), Ho et al (US 20220262908), Huang et al (US 20220093757), and Chen et al (US 20210296451) as devices with connective structures deposited through the ILD layer over the gate, source and drain region.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 572-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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