Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 11/18/2024 and 12/29/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-11 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US20230275080A1; Chen et al.; (hereinafter “Chen”) in view of US20230297754A1; Wang et al.; (hereinafter “Wang”).
Regarding Claim 1, Chen teaches an integrated circuit, comprising:
a first cell region including at least a first set of transistors, the first cell region extending in a first direction and having a first height in a second direction different from the first direction (Figures 1A-B, transistor #T1 extends in cell region between gates along x-y direction), the first set of transistors comprising:
a first active region (#112-113) extending in the first direction, and being on a first level (#OD_1);
a second cell region including at least a second set of transistors, the second cell region extending in the first direction and having the first height in the second direction (transistor #T2 extends in cell region between gates along x-y direction), the second set of transistors comprising:
a second active region (#114-115) extending in the first direction, being on the first level (#OD_1), and being separated from the first active region in the second direction (#114 is separated from #113 by gate region);
a first set of conductors (#M01-M03) extending in the first direction, being on a first metal layer (#M0, metal zero layer) above a front-side of a substrate (#121), overlapping the first active region (#112-113) or the second active region (#114-115), and being coupled to at least the first set of transistors (#T1) or the second set of transistors (#T2); and
a second set of conductors (#BM0_1-2) extending in the first direction, being on a second metal layer (#BM0, back-side metal zero layer) below a back-side of the substrate (#122), being coupled to at least the first set of transistors (#T1), the second set of conductors (#BM0_1-2) configured to supply at least the supply voltage or the reference supply voltage ([0039]);
the first set of transistors have a first size, and the second set of transistors have a second size (transistors #T1/T2 have dimensions of active regions #112-113/114-115 along x-z direction).
Chen does not explicitly teach the first set of conductors configured to supply at least a supply voltage or a reference supply voltage; and the second set of transistors have a second size different from the first size;
However, Wang teaches a comparable integrated circuit comprising a first set of conductors configured to supply at least a supply voltage or a reference supply voltage ([0088-0089], conductive patterns #220 on metal zero layer #M0 correspond to supply voltage VDD or reference supply voltage VSS); and a second set of transistors (#506, Figures 5A-B, cell layout) have a second size (#W2a-W2b, width) different from a first size (width #W2a-W2a of cell #504).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Chen with the teaching of Wang in order to enable tuning of speed and driving strength of the conducting devices/transistors according to Wang, [0059-0065].
Regarding Claim 2, Chen in view of Wang teaches the integrated circuit as described in claim 1, wherein Chen further teaches the first set of transistors (Figures 1A-B) comprises:
a first transistor (#T1); and
a first contact (#MD_1) extending in the second direction, overlapping the first active region (#112-113), and being on a third metal layer different from the first metal layer and the second metal layer (#MD layer is separated from layers #M0 and #BM0), the first contact (#MD) being electrically coupled to a first source (#113) of the first transistor.
Regarding Claim 3, Chen in view of Wang teaches the integrated circuit as described in claim 2, wherein Chen further teaches the first set of transistors (Figure 1A) further comprises:
a second contact (#VB_1) extending in the second direction, being overlapped by the first active region (#112-113), and being on a fourth metal layer different from the first metal layer, the second metal layer and the third metal layer (#VB layer is different from layers #M0, #BM0 and #MD), the second contact (#VB_1) being electrically coupled to the first source (#113) of the first transistor.
Regarding Claim 4, Chen in view of Wang teaches the integrated circuit as described in claim 3, wherein Chen further teaches the second set of transistors (Figures 1A-B) comprises:
a second transistor (#T2); and
a third contact (#MD_2) extending in the second direction, overlapping the second active region (#114-115), and being on the third metal layer (#MD), the third contact being electrically coupled to a first source (#114) of the second transistor.
Regarding Claim 5, Chen in view of Wang teaches the integrated circuit as described in claim 1, wherein Chen further teaches the first active region (#112-113) has a first width in the second direction, the first width being the first size; and
the second active region (#114-115) has a second width in the second direction, the second width being the second size, and being different from the first width (see rejection of claim 1 regarding transistors with different sizes).
Regarding Claim 6, Chen in view of Wang teaches the integrated circuit as described in claim 1, wherein Chen further teaches a first via (#MD_2, Figures 1A-B) between a first conductor (#M01) of the first set of conductors and a first conductor (#BM0_1) of the second set of conductors, the first via (#MD_2) being next to the second cell region (#T2).
Regarding Claim 7, Chen in view of Wang teaches the integrated circuit as described in claim 6, wherein Chen further teaches a second via (#VD-2) between the first conductor (#M01) of the first set of conductors and the first conductor (#BM0_1) of the second set of conductors, the second via (#VD-2) being next to the first via (#MD_2), and the first via (#MD_2) being between the second via (#VD-2) and the second cell region (#T2).
Regarding Claim 8, Chen in view of Wang teaches the integrated circuit as described in claim 1, wherein Chen further teaches a first conductor (#MD-1, Figure 1A) extending in the second direction, being on a third metal layer (#MD) above the front-side of the substrate (#121), the third metal layer being different from the first metal layer and the second metal layer (#MD layer is separated from layers #M0 and #BM0), the first conductor (#MD-1) overlapping the first set of conductors (#M01-M03) and the second set of conductors (#BM0_1-2); and
a first via (#VD-1) between the first conductor (#MD-1) and a first conductor (#M01) of the first set of conductors, the first via electrically coupling the first conductor and the first conductor of the first set of conductors (#VD-1 connects #MD-1 and #M01) together.
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Regarding Claim 9, Chen in view of Wang teaches the integrated circuit as described in claim 8, Chen further teaches a second conductor (#M1-1, Figure 4F of Chen annotated) extending in the first direction, being on a fourth metal layer (#M1) above the front-side of the substrate (#121), the fourth metal layer being different from the first metal layer, the second metal layer and the third metal layer (#M1 is separated from #M0, #BM0 and #MD), the second conductor overlapping the first conductor, the first set of conductors and the second set of conductors (#M1-1 overlaps #MD, #M01-M03 and #BM0_1-2); and
a second via (#VIA-0) between the second conductor (#M1-1) and the first conductor (#MD), the second via electrically coupling the second conductor and the first conductor together (#VIA-0 connects #M1-1 and #MD).
Regarding Claim 10, Chen in view of Wang teaches the integrated circuit as described in claim 9, Chen further teaches a third conductor (#M2_3, Figure 4F of Chen annotated) extending in the second direction, being on a fifth metal layer (#M2) above the front-side of the substrate (#121), the fifth metal layer being different from the first metal layer, the second metal layer, the third metal layer and the fourth metal layer (#M2 is separated from #M0, #BM0, #MD and #M1), the third conductor overlapping the first conductor, the second conductor, the first set of conductors and the second set of conductors (#M2_3 overlaps #MD, #M1-1, #M01-M03 and #BM0_1-2); and
a third via (#VIA-1) between the third conductor (#M2_3) and the second conductor (#M1-1), the third via electrically coupling the third conductor and the second conductor together (#VIA-1 connects #M1-1 and #M2_3).
Regarding Claim 11, Chen teaches an integrated circuit, comprising:
a first set of transistors (#T1, Figures 1A-B) in a first region, the first region extending in a first direction and having a first height in a second direction different from the first direction (#T1 extends in cell region between gates along x-y direction), the first set of transistors comprising:
a first active region (#112-113) extending in the first direction, and being on a first level (#OD_1);
a second set of transistors (#T2) in a second region, the second region extending in the first direction and having a second height in the second direction (#T2 extends in cell region between gates along x-y direction), the second set of transistors comprising:
a second active region (#114-115) extending in the first direction, being on the first level (#OD_1), and being separated from the first active region in the second direction (#114 is separated from #113 by gate region);
a first set of conductors (#M01-M02) extending in the first direction, being on a first metal layer (#M0) above a front-side of a substrate (#121), overlapping the first active region (#112-113), and being coupled to at least the first set of transistors (#T1), each conductor of the first set of conductors being separated from each other by a first pitch in the second direction (conductive patterns #M01-M02 dispose separated from each other); and
a second set of conductors (Figure 3, #M04-M05) extending in the first direction, being on the first metal layer (#M0), being coupled to at least the second set of transistors (Figure 3 or 4D), each conductor of the second set of conductors being separated from each other by a second pitch in the second direction (conductive patterns #M04-M05 dispose separated from each other), the second set of conductors being separated from the first set of conductors in the second direction (#M01-M02 and #M04-M05 are separated),
wherein the first set of transistors have a first size, and the second set of transistors have a second size different from the first size (transistors #T1/T2 have dimensions of active regions #112-113/114-115 along x-z direction).
Chen does not explicitly teach the first set of conductors and the second set of conductors configured to supply at least a supply voltage or a reference supply voltage the second height being different from the first height; the second set of transistors have a second size different from the first size; and the second pitch being different from the first pitch.
However, Wang teaches a comparable integrated circuit comprising a first set of conductors and a second set of conductors configured to supply at least a supply voltage or a reference supply voltage ([0088-0089], conductive patterns #220a-e on metal zero layer #M0 correspond to supply voltage VDD or reference supply voltage VSS); a second height (#H2, Figure 1) of a set of second set of transistors (#104a) being different from a first height (#H1) of a first set of transistors (#102a); the second set of transistors (#506, Figures 5A-B, cell layout) have a second size (#W2a-W2b, width) different from a first size of the first set of transistors (width #W2a-W2a of cell #504); and a second pitch of a second set of conductors being different from a first pitch of a first set of conductors ([104], one or more conductive patterns of a set of conductive patterns #230/220 can have a different pitch from the adjacent patterns having the same pitch).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Chen with the teaching of Wang in order to enable tuning of speed and driving strength of the conducting devices/transistors according to Wang, [0059-0065].
Regarding Claim 20, Chen teaches a method of forming an integrated circuit, the method comprising:
fabricating a first set of transistors (#T1, Figures 1A-B) in a front-side of a substrate (#121) in a first row, the first row extending in a first direction, the first set of transistors including at least a first transistor, the first set of transistors having a first size (transistor #T1 has a dimension of active regions #112-113 extending along x-z direction);
fabricating a second set of transistors (#T2) in the front-side of the substrate (#121) in a second row, the second row extending in the first direction, and being separated from the first row in a second direction different from the first direction (#T1 and #T2 are separated), the second set of transistors including a second transistor, the second set of transistors having a second size (transistor #T2 has a dimension of active regions #114-115 extending along x-z direction);
electrically coupling a first set of conductors (#M01-M03) on the front-side of the substrate (#121) to at least the first set of transistors (#T1) or the second set of transistors (#T2), wherein electrically coupling the first set of conductors on the front-side of the substrate to at least the first set of transistors or the second set of transistors comprises:
depositing a first conductive material (Figure 4D, [0070]) on the front-side of the substrate (#121) on a first metal level (#M0) thereby forming the first set of conductors (#M01-M05), the first set of conductors being electrically coupled to at least the first set of transistors (#T1) or the second set of transistors (#T2); and
electrically coupling a second set of conductors (#BM0_1-2, Figures 4A-B) on a back-side of the substrate (#122) to at least the first set of transistors (#T1), wherein electrically coupling the second set of conductors on the back-side of the substrate to at least the first set of transistors comprises:
depositing a second conductive material ([0067]) on the back-side of a thinned substrate (#122) on a second metal level (#M0) thereby forming the second set of conductors (#BM0_1-2), the second set of conductors being electrically coupled to at least the first set of transistors (#T1).
Chen does not teach the second set of transistors having the second size different from the first size.
However, Wang teaches a method of forming a comparable integrated circuit comprising a second set of transistors (#506, Figures 5A-B, cell layout) having a second size (#W2a-W2b, width) different from a first size of a first set of transistors (width #W2a-W2a of cell #504).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Chen with the teaching of Wang in order to enable tuning of speed and driving strength of the conducting devices/transistors according to Wang, [0059-0065].
Allowable Subject Matter
Claims 12-19 are allowed. The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 12, the most relevant prior art of record, Chen in view of Wang discloses the integrated circuit as described in claim 11, Chen further discloses a third set of conductors extending in the first direction (#BM0_1, Figures 1A-B or 4A-F), being on a second metal layer (#BM0) below a back-side of the substrate (#122), being coupled to at least the first set of transistors (#T1), the second set of conductors configured to supply at least the supply voltage or the reference supply voltage ([0039]); and
a fourth set of conductors (#BM0_2) extending in the first direction, being on the second metal layer (#BM0), being coupled to at least the second set of transistors (Figure 3 or 4B), the fourth set of conductors configured to supply at least the supply voltage or the reference supply voltage ([0039]), the fourth set of conductors being separated from the third set of conductors in the second direction.
None of the prior art of record discloses or makes obvious the limitations: “each conductor of the third set of conductors being separated from each other by the first pitch in the second direction” and “each conductor of the fourth set of conductors being separated from each other by the second pitch in the second direction” recited in claim 12, in combination with the other claimed elements.
Therefore, claim 12 is allowed, and claim 13-19 are allowed at least by virtue of their dependency on claim 12.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US20240332196A1 – Figure 1A-5C
US20220130760A1 – Figures 1B, 3A-5B
US20170294448A1 – Figures 1, 5-7
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/TIEN TRAN/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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