DETAILED ACTION
Election/Restriction
Applicant's election without traverse of Group II, claims 1-9, and newly added claims 21 - 31 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6 - 8 are rejected under 35 U.S.C. 103 as being unpatentable over PARK et al. (2024/0213133) in view of SHIH (2023/0060355).
With regard to claim 1, PARK et al. disclose a method (for example, see figs. 3, 5 -13) comprising:
forming an interconnect structure (pad structures 102, fig. 5 functions as an interconnect structure) over a substrate (1000), the interconnect structure comprising a contact pad (one of pads 102 is a contact pad) embedded in a dielectric layer (101);
forming a first insulating layer (111) over the interconnect structure (pad structures 102 functions as an interconnect structure);
forming a first opening (OP1, fig. 5) through the first insulating layer (111) to expose the contact pad (102);
depositing a seed layer (SL, fig. 6) over the first insulating layer (111) and in the first opening (OP1);
forming a sacrificial material (a photoresist pattern PR, fig. 6, functions as a sacrificial material) over the seed layer (SL, fig. 6);
patterning the sacrificial material (PR, fig. 6) to expose the seed layer (SL, fig. 6) in the first opening (OP1) and to form a second opening (PO, fig. 6) exposing the seed layer (SL, fig. 6) over the first insulating layer (111);
depositing conductive material (120, fig. 7) to form a first redistribution line (referred to as “120A” by examiner’s annotation shown in fig. 7 below; wherein the conductive portions120A, forming in the redistribution structure 100, fig. 3, functions as a first redistribution line) in the first opening (OP1) and a second redistribution line (referred to as “120B” by examiner’s annotation shown in fig. 7 below; wherein the conductive portions120B, forming in the redistribution structure 100, fig. 3, functions as a first redistribution line) in the second opening (PO);
removing the sacrificial material (PR, fig. 9); and
attaching an integrated circuit die (200, fig. 13) to the first redistribution line (120A) and the second redistribution line (120B).
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PARK et al. does not clearly disclose forming active devices over a semiconductor substrate wherein the insulating layer is the passivation insulating layer.
However, SHIH discloses forming active devices (for example, see paragraph [0040]) over a semiconductor substrate (the first semiconductor wafer 100 includes a substrate 101, so the substrate 101 functions as a semiconductor substrate; for example, see paragraph [0029]) wherein the insulating layer (insulating layers 113, 123) is the passivation insulating layer (insulating layers 113, 123 made of silicon oxide, silicon nitride, for example, paragraph [0042], and is formed the same as that of applicant, thus the insulating layer of SHIH has the same functions, passivation material, as the claimed invention. Although the applicant uses terms different to those of SHIH to label/describe the claimed invention, this does not result in any structural difference between the claimed invention and the prior art. The use different terminology to describe the plurality of elements that constitute an integrated circuit as this is just a writing style and the way in which a structural limitation is expressed does not affect the configuration of the described elements.)
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the PARK et al.’s device to have active devices over a semiconductor substrate wherein the insulating layer is the passivation insulating layer. as taught by SHIH in order to minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 6, PARK et al. disclose attaching the integrated circuit die comprises: direct bonding a first die connector (one of the contacts SL functions as a first die connector) of the integrated circuit die to the first redistribution line (120A); and direct bonding a second die connector (one of the contact 130 functions as a first die connector) of the integrated circuit die to the second redistribution line (120B).
With regard to claim 7, PARK et al. disclose attaching the integrated circuit die comprises direct bonding a third redistribution line (one of the contacts 130 functions as a third redistribution line) of the integrated circuit die to the first redistribution line (120A) and the second redistribution line (120B).
With regard to claim 8, PARK et al. disclose the second redistribution line (120B) functions as a dummy redistribution line in order to secure the electrical connection efficiency Although the applicant uses terms different to those of PARK et al. to label/describe the claimed invention, this does not result in any structural difference between the claimed invention and the prior art. The use different terminology to describe the plurality of elements that constitute an integrated circuit as this is just a writing style and the way in which a structural limitation is expressed does not affect the configuration of the described elements.
Claims 21 – 24, 27 - 30 are rejected under 35 U.S.C. 103 as being unpatentable over Hashiguchi (12087795) in view of KWON (20240105541).
With regard to claim 21, Hashiguchi (12087795) disclose a method (for example, see fig. 14) comprising:
forming an interconnect structure (59e) over an active device layer (an active device layer having transistor Tr) of a first semiconductor substrate (50e);
forming conductive lines (67e) over the interconnect structure (59e);
forming a passivation layer (an insulating layer 69e, is formed the same material as the insulating layer 35e, wherein the insulating layer 35e made of silicon nitride, for example, column 13, lines 39 - 45, and is formed the same as that of applicant, thus the insulating layer of Hashiguchi (12087795) has the same functions, passivation material, as the claimed invention. Although the applicant uses terms different to those of Hashiguchi (12087795) to label/describe the claimed invention, this does not result in any structural difference between the claimed invention and the prior art. The use different terminology to describe the plurality of elements that constitute an integrated circuit as this is just a writing style and the way in which a structural limitation is expressed does not affect the configuration of the described elements.).
and over the interconnect structure (59e);
planarizing (for example, column 13, 15, lines 58, 59) the insulating layer (69e) and upper portions of the conductive lines (67e) such that upper surfaces (41e) of the conductive lines (67e) are substantially coplanar with an upper surface (71e) of the passivation layer (69e); and
bonding a first integrated circuit die (7e) comprising the first semiconductor substrate (50e), the interconnect structure (59e), the conductive lines (67e), and the passivation layer (69e) to a second integrated circuit die (2e), the bonding comprising forming metal-to-metal bonds between the conductive lines (67e) of the first integrated circuit die (7e) and conductive features (33e) of the second integrated circuit die (2e) and forming dielectric-to-dielectric bonds (bonds at interfaces) between the insulating layer (69e) of the first integrated circuit die (7e) and a dielectric layer (35e) of the second integrated circuit die (2e).
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Hashiguchi (12087795) does not clearly disclose the conductive lines are redistribution conductive lines and the insulating layer is over the redistribution lines.
However, KWON discloses the conductive lines (164) are redistribution conductive lines and an insulating layer (a layer 160 including an insulating layer) over the redistribution lines (164). (for example, see fig. 1).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Hashiguchi (12087795)’s device to have the conductive lines are redistribution conductive lines and the insulating layer is over the redistribution lines as taught by KWON in order to secure the electrical connection efficiency of the semiconductor device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 22, Hashiguchi (12087795) disclose the conductive lines (67e) inherently having convex upper surfaces prior to the planarizing, and wherein the planarizing removes the convex upper surfaces in order to secure the electrode bonding. (for example, column 13, 15, lines 58, 59).
With regard to claim 23, Hashiguchi (12087795) disclose the conductive features (33e) of the second integrated circuit die (2e) are bond pads, and wherein the dielectric layer (35e) of the second integrated circuit die (2e) functions as a dielectric bond layer in which the bond pads (33e) are embedded.
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With regard to claim 24, Hashiguchi (12087795) disclose the conductive features (33e) of the second integrated circuit die (2e) are second conductive lines (33e) embedded in a second passivation layer (the insulating layer 35e made of silicon nitride, for example, column 13, lines 39 - 45, and is formed the same as that of applicant, thus the insulating layer of Hashiguchi (12087795) has the same functions, passivation material, as the claimed invention. Although the applicant uses terms different to those of Hashiguchi (12087795) to label/describe the claimed invention, this does not result in any structural difference between the claimed invention and the prior art. The use different terminology to describe the plurality of elements that constitute an integrated circuit as this is just a writing style and the way in which a structural limitation is expressed does not affect the configuration of the described elements.), the second passivation layer (35e) being the dielectric layer of the second integrated circuit die (2e). KWON discloses the conductive lines (254) are redistribution conductive lines wherein the insulating layer (a layer 250 including the insulating layer) over the redistribution lines (254). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Hashiguchi (12087795)’s device to have the conductive lines are redistribution conductive lines wherein the insulating layer over the redistribution lines as taught by KWON in order to secure the electrical connection efficiency of the semiconductor device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 27, Hashiguchi (12087795) discloses a method (for example, see fig. 14) comprising:
forming a first integrated circuit die (7e), the forming of the first integrated circuit die (7e) comprising:
forming a first interconnect structure (59e) over an active surface of a first semiconductor substrate (50e);
forming first conductive lines (67e) over the first interconnect structure (59e);
forming a first passivation layer (an insulating layer 69e, is formed the same material as the insulating layer 35e, wherein the insulating layer 35e made of silicon nitride, for example, column 13, lines 39 - 45, and is formed the same as that of applicant, thus the insulating layer of Hashiguchi (12087795) has the same functions, passivation material, as the claimed invention. Although the applicant uses terms different to those of Hashiguchi (12087795) to label/describe the claimed invention, this does not result in any structural difference between the claimed invention and the prior art. The use different terminology to describe the plurality of elements that constitute an integrated circuit as this is just a writing style and the way in which a structural limitation is expressed does not affect the configuration of the described elements.); and
planarizing the first passivation layer (69e) such that upper surfaces (41e) of the first conductive lines (67e) are substantially coplanar with an upper surface (71e) of the first passivation layer (69e);
forming a second integrated circuit die (7e), the forming of the second integrated circuit die (7e) comprising:
forming a second interconnect structure (31e) over (over when the device of fig. 14 is flipped over; over a lower surface; or overlapping is over) an active surface of a second semiconductor substrate (20e);
forming second conductive lines (33e) over (over when the device of fig. 14 is flipped over; over a lower surface; or overlapping is over) the second interconnect structure (31e);
forming a second passivation layer (the insulating layer 35e made of silicon nitride, for example, column 13, lines 39 - 45, and is formed the same as that of applicant, thus the insulating layer of Hashiguchi (12087795) has the same functions, passivation material, as the claimed invention. Although the applicant uses terms different to those of Hashiguchi (12087795) to label/describe the claimed invention, this does not result in any structural difference between the claimed invention and the prior art. The use different terminology to describe the plurality of elements that constitute an integrated circuit as this is just a writing style and the way in which a structural limitation is expressed does not affect the configuration of the described elements.).
and planarizing (for example, column 13, 15, lines 58, 59) the second passivation layer (35e) such that upper surfaces (41e) of the second conductive lines (33e) are substantially coplanar with an upper surface of the second passivation layer (35e); and
bonding the first integrated circuit die (7e) to the second integrated circuit die (2e), the bonding comprising forming metal-to-metal bonds (interface bonds) between the first conductive lines (67e) and the second conductive lines (33e) and forming dielectric-to-dielectric bonds (interface bonds) between the first passivation layer (69e) and the second passivation layer (35e).
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Hashiguchi (12087795) does not clearly disclose the conductive lines are redistribution conductive lines wherein the insulating layers over the redistribution lines.
However, KWON discloses the conductive lines (164, 254) are redistribution conductive lines wherein the insulating layers (layers 160, 250 including insulating layers) over the redistribution lines (164, 254). (for example, see fig. 1).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Hashiguchi (12087795)’s device to have the conductive lines are redistribution conductive lines wherein the insulating layers over the redistribution lines as taught by KWON in order to secure the electrical connection efficiency of the semiconductor device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 28, Hashiguchi (12087795) discloses during the bonding, one of the first integrated circuit die (7e) and the second integrated circuit die (2e) is in wafer form and the other of the first integrated circuit die (7e) and the second integrated circuit die (2e) has been singulated from a wafer.
With regard to claim 29, KWON discloses the bonding comprises: inherently pressing the second integrated circuit die against the first integrated circuit die at about room temperature (any temperature to be a room temperature); and inherently annealing (any thermal temperature) the first integrated circuit die (100) and the second integrated circuit die (200) to form the metal-to-metal bonds and the dielectric-to-dielectric bonds in order to secure the electrode bonding efficiency.
With regard to claim 30, Hashiguchi (12087795) disclose in plan views (cross-sectional views including plan views) at least one of the first conductive lines (67e) has a different size, shape, than a corresponding one of the second conductive lines (33e) bonded thereto, and wherein a portion of the at least one of the first conductive lines (67e) overextends the corresponding one of the second conductive lines (33e) and is in physical contact with the second passivation layer (35e).
Allowable Subject Matter
5. Claims 2 - 5, 9, 25, 26, 31 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 2 - 5, 9, 25, 26, 31 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as after removing the sacrificial material, forming a second passivation layer over the first redistribution line and the second redistribution line; and planarizing the second passivation layer to be level with the first redistribution line and the second redistribution line as recited in claim 2, before depositing the seed layer, depositing a barrier layer along the first passivation layer and the contact pad as recited in claim 9, the passivation layer comprises depositing a nitride layer over the redistribution lines, depositing an oxide layer over the nitride layer, and depositing a bulk oxide layer over the oxide layer as recited in claim 25, in plan views the at least one of the first redistribution lines has a rectangular shape comprising four corners, and the corresponding one
of the second redistribution lines has an L-shape comprising six corners, and wherein the portion of the at least one of the first redistribution lines that overextends the corresponding one of the second redistribution lines comprises a region of the rectangular shape that lies outside the L-shape in the plan views as recited in claim 31.
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812
Prosecution Insights