Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This office action is in response application 18/587437 filed on 02/26/24.
Information Disclosure Statement
The information disclosure statement (IDS) submitted filed before the mailing of a first Office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97(b) (3). Accordingly, the information disclosure statement is being considered by the examiner.
Summary of claims
Claims 1-28 are pending.
Claims 1-8 are canceled.
Claims 9-28 are rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
Claims 9-28 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Or-Bach et al. (US Pub. 2013/0049577).
As to claim 9 the prior art teach a method of manufacturing an integrated circuit, comprising:
performing a layout versus schematic check of the integrated circuit (see fig 89a-d paragraph 0329-0332 view layout and schematic of array);
determining if a first cell of a layout of the integrated circuit and a second cell of the layout of the integrated circuit have a distributed layout style that electrically coupled gate electrode fingers are distributed in the first cell and the second cell, the first cell being on a first edge of a cell array, and the second cell being adjacent to the first cell and away from the first edge of the cell array (see fig 42-47 paragraph 0468-0472, cells schematic layout);
determining if the layout of the integrated circuit comprises a buffer zone outside of the cell array adjacent to the first edge, the buffer zone comprising one or more dummy cells (see fig 16-19 paragraph 0217-0222);
generating a modified layout by inserting the buffer zone outside of the cell array adjacent to the first edge if determined that the layout fails to include the buffer zone (see fig 70-71 81a-f paragraph 0411-0417 and 0429-0435);
and performing a design rule check on the modified layout, wherein at least one of the above operations is performed by a processor (see fig 76-80 paragraph 0443-0449);
and fabricating the integrated circuit based on the modified layout (see fig 42-46 paragraph 0469-0478).
As to claim 10 the prior art teach wherein performing the layout versus schematic check of the integrated circuit comprises: comparing a schematic design of the integrated circuit to the layout of the integrated circuit to determine whether the layout includes features of the schematic design (see fig 89a-d paragraph 0330-0335).
As to claim 11, the prior art teach further comprising: generating a schematic design of the integrated circuit and the layout of the integrated circuit (see fig 44-47 paragraph 0469-0471).
As to claim 12 the prior art teaches wherein performing the design rule check on the modified layout comprises:
determining a pattern density gradient at the first cell or the second cell of the integrated circuit (see fig 50-55 paragraph 0483-0489);
and performing smart dummy insertion to revise the modified layout based on layout style information and an array edge information in response to the pattern density gradient at the first cell or the second cell exceeding a first threshold (see fig 52-58 paragraph 0489-0495).
As to claim 13, 15 and 23 the prior art teaches modified layout comprises:
physically creating at least one mask based on the modified layout of the integrated circuit (see fig 86-88 paragraph 0328-0331);
and fabricating the integrated circuit based on the at least one mask (see fig 86-88 paragraph 0332-0338).
As to claims 14 the prior art teaches a method of making a semiconductor device comprising:
determining if a first cell of a layout design of the semiconductor device and a second cell of the layout design of the semiconductor device have a distributed layout style that a plurality of electrically coupled gate electrode fingers are distributed in the first cell and the second cell, the first cell being on an edge of a cell array, and the second cell being adjacent to the first cell and away from the edge of the cell array (see fig 42-47 paragraph 0468-0472, cells schematic layout);
determining if the layout design of the semiconductor device comprises a buffer zone outside of the cell array adjacent to the edge, the buffer zone comprising one or more dummy cells see fig 16-19 paragraph 0217-0222);
modifying the layout design by inserting the buffer zone outside of the cell array adjacent to the edge if determined that the layout design does not include the buffer zone (see fig 70-71 81a-f paragraph 0411-0417 and 0429-0435);
and performing a design rule check on the modified layout design, wherein at least one of the above operations is performed by a computer (see fig 76-80 paragraph 0443-0449);
and fabricating the semiconductor device based on the modified layout design (see fig 42-46 paragraph 0469-0478).
As to claim 16 and 24 the prior art teaches modifying the layout design by reducing an area of the buffer zone if determined that the layout design includes the buffer zone and, if determined that the first cell and the second cell have the distributed layout style (see fig 70-71 81a-f paragraph 0430-0438).
As to claim 17 and 25 the prior art teaches performing a resistance-capacitance extraction on the layout design of the semiconductor device or the modified layout design of the semiconductor device (see fig 76-80 paragraph 0445-0451)
As to claim 18 and 26 the prior art teaches wherein performing the design rule check on the modified layout design comprises: determining a pattern density gradient at the first cell or the second cell of the semiconductor device (see fig 83-86 paragraph 0407-0412).
As to claim 19-21 and 27 the prior art teaches wherein performing the design rule check on the modified layout design further comprises:
performing smart dummy insertion to revise the modified layout design based on layout style information and an array edge information, if the pattern density gradient at the first cell or the second cell exceeds a threshold (see fig 76-80 paragraph 0453-0459);
wherein the threshold is 10% (see fig 76-80 paragraph 0458-0463).
As to claim 22 the prior art teaches a method of making a semiconductor device comprising:
determining if a first cell of a layout of the semiconductor device and a second cell of the layout of the semiconductor device have a distributed layout style, the distributed layout style including a plurality of electrically coupled gate electrode fingers that are distributed in the first cell and the second cell, the first cell being on an edge of a first cell array, and the second cell being adjacent to the first cell and separated from the edge of the first cell array (see fig 42-47 paragraph 0468-0472, cells schematic layout);
determining if the layout of the semiconductor device comprises a first buffer zone outside of the first cell array adjacent to the edge, the first buffer zone comprising a set of dummy cells (see fig 16-19 paragraph 0217-0222);
changing the layout by placing the first buffer zone outside of the first cell array adjacent to the edge if determined that the layout does not include the first buffer zone (see fig 70-71 81a-f paragraph 0411-0417 and 0429-0435);
and performing a design rule check on the changed layout, wherein at least one of the above operations is performed by a computer (see fig 76-80 paragraph 0443-0449);
and fabricating the semiconductor device based on the changed layout (see fig 42-46 paragraph 0469-0478).
As to claim 28 the prior art teaches further comprising: performing a layout versus schematic check of the semiconductor device, wherein performing the layout versus schematic check of the semiconductor device comprises: comparing a schematic design of the semiconductor device to the layout of the semiconductor device to determine whether the layout includes features of the schematic design (see fig 89a-d paragraph 0334-0341).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH C TAT whose telephone number is 571 272-1908. The examiner can normally be reached on flex 7:00Am-8PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BINH C TAT/Primary Examiner, Art Unit 2851