DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Election/Restrictions 3
III. Specification 3
IV. Drawings 3
V. Claim Rejections - 35 USC § 112 4
A. Claims 17-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. 4
VI. Claim Rejections - 35 USC § 102 5
A. Claim 11 is rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2023/0066291 (“Lin-291”). 5
B. Claims 11 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0310472 (“Huang”). 8
VII. Claim Rejections - 35 USC § 103 10
A. Claims 1-3, 6, 8, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of US 2014/0131860 (“Kanda”). 10
C. Claims 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Kanda, as applied to claims 1 and 17, above, and further in view of US 2001/0017373 (“Nishibayashi”). 17
VIII. Allowable Subject Matter 18
IX. Pertinent Prior Art 21
Conclusion 22
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Election/Restrictions
Applicant’s election of invention group I without traverse in the Response filed 08/03/2026 is acknowledged. In view of Applicant’s amendment, also filed 08/03/2026, amending claims 17-20 such that they fall within invention group I, thereby making all of claims 1-20 fall within invention group I, the Restriction mailed 06/01/2026 is currently rendered moot.
III. Specification
The correction to the specification filed 08/03/2026 are acceptable.
IV. Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, each of the following must be shown or the feature(s) canceled from the claim(s):
(1) In claims 1 and 16, “the third metal features 412, 413 are electrically connected to an S/D region 204b or a gate stack 208 of the transistor devices 205”.
(2) In claim 17, “a device layer 200 over a device substrate 202”, which is contrary to all of the figures. Instead, the figures show that the device layer 200 includes a device substrate 202. (See e.g. Instant Specification at ¶ 42.)
(3) In claims 7, 18, and 19, the aluminum bond pads in the RDL structure 602, which is the “AP layer 602”.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
V. Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
A. Claims 17-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 17 recites the limitation “the electrical lines and vias” in line 11. There is insufficient antecedent basis for this limitation in the claim.
Claim 17 recites the limitation “the backside electrical lines and vias” in lines 18-19. There is insufficient antecedent basis for this limitation in the claim.
Claims 18-20 are rejected for including the same indefinite feature by depending from claim 17, either directly or indirectly.
VI. Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
A. Claim 11 is rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2023/0066291 (“Lin-291”).
The applied reference has a common Assignee with the Instant Application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
In addition to including any one of the statements pursuant to 35 U.S.C. 102(b)(2)(A) through (C), (supra), to overcome Lin-291 as prior art available under 35 USC 102(a)(2), it is still applicable as prior art under 35 U.S.C. 102(a)(1) that cannot be excepted under 35 U.S.C. 102(b)(2)(C). In this instance, Applicant may rely on the exception under 35 U.S.C. 102(b)(1)(A) to overcome this rejection under 35 U.S.C. 102(a)(1) by a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application, and is therefore not prior art under 35 U.S.C. 102(a)(1). Alternatively, applicant may rely on the exception under 35 U.S.C. 102(b)(1)(B) by providing evidence of a prior public disclosure via an affidavit or declaration under 37 CFR 1.130(b).
With regard to claim 11, Lin-291 discloses, generally in Figs. 2-3,
11. (Original) An integrated circuit (IC) structure, comprising:
[1] a device layer 106 [¶¶ 13, 14] having transistor devices, the transistor devices having channel regions between source/drain (S/D) regions 110 and gate stacks 122 over the channel regions [¶¶ 13, 16];
[2a] a frontside interconnect structure 120, 140/142/144/146/148, 158 [¶¶ 16-22, 24-29] on a front side of the device layer 106, wherein
[2b] the frontside interconnect structure includes 120, 140/142/144/146/148, 158 first metal features 134, 142, 144, 148 [¶¶ 16-22] and second metal features 176, 178 [¶¶ 24-29] embedded in an intermetal dielectric (IMD) layer 136, 140, 152, 154, 160 [¶¶ 17, 23, 24],
[2c] the first 134, 142, 144, 148 and second 176, 178 metal features are isolated from each other by the IMD layer 136, 140, 152, 154, 160,
[2d] the first metal features 134, 142, 144, 148 are electrically connected to an S/D region 110 or a gate stack 122 of the transistor devices, and
[2e] the second metal features 176, 178 are electrically isolated from the transistor devices [because the metal features 176, 178 are dummy features (¶ 24)];
[3] a bonding oxide layer [at interface between bonding layer 166 and the top surface 172 of the topmost 162 of 158] over the frontside interconnect structure 120, 140/142/144/146/148, 158 [infra]; and
[4] a substrate 168 [¶ 28] over the bonding oxide layer.
With regard to feature [3] of claim 11, Lin-291 states,
[0026] According to some embodiments, the thermally conductive material 170 comprises aluminum (Al), aluminum nitride (AlN), or other bonding material suitable for bonding and for heat transfer. The material is applied to an upper surface 172 of the first heat conductor 158 by at least one of thermal oxidation, PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, MBE, LPE, spin coating, oxidation, a passivation process, or other suitable techniques.
(Lin-291: ¶ 26; emphasis added; emphasis added)
The use of oxidation to bond 170 to the top surface 172 of 158 would inherently, necessarily result in a bonding oxide layer at interface between bonding layer 166 and the top surface 172 of the topmost 162 of 158. As such, the burden of proof is shifted to Applicant to prove the contrary. (See MPEP 2112(I)-(V).)
In addition, Lin-291 states,
[0027] A bonding process for bonding the heat sink 168 to the first heat conductor 158 includes at least one or more of adhesive bonding, surface activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, thermocompression bonding, reactive bonding, transient liquid phase diffusion bonding, or other suitable bonding processes.
(Lin-291: ¶ 27; emphasis added)
Glass is silicon dioxide.
This is all of the limitations of claim 11.
B. Claims 11 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0310472 (“Huang”).
With regard to claim 11, Huang discloses, generally in Figs. 30A-30C,
11. (Original) An integrated circuit (IC) structure, comprising:
[1] a device layer 115 [e.g. ¶ 88] having transistor devices [¶ 98: “a device includes a device layer [115] comprising a first transistor”], the transistor devices having channel regions 55 between source/drain (S/D) regions 90/92 and gate stacks 96/98(100/102) over the channel regions 55 [¶¶ 12-16, 53, 58; Figs. 1; 13A-13C, 17A-17C];
[2a] a frontside interconnect structure 120 [¶¶ 70-71, 93] on a front side of the device layer 115, wherein
[2b] the frontside interconnect structure 120 includes first metal features 122 [¶¶ 70-72] and second metal features 142 embedded in an intermetal dielectric (IMD) layer 124 [¶¶ 70, 89, 93 (infra)],
[2c] the first 122 and second metal features 142 are isolated from each other by the IMD layer 124 [¶ 88 (infra) and as shown in Figs. 30A-30C],
[2d] the first metal features 122 are electrically connected to an S/D region 90/92 [as shown in Fig. 30A by conductive contact 112 (¶ 66)] or a gate stack 100/102 [as shown in Figs. 30A-30B] of the transistor devices, and
[2e] the second metal features 142 are electrically isolated from the transistor devices [¶ 88 (infra)];
[3] a bonding oxide layer 152 [¶¶ 74-75] over the frontside interconnect structure 120; and
[4] a substrate 150 over the bonding oxide layer [¶¶ 74-75].
With regard to features [2a]-[2c] and [2d] of claim 11, specifically the claimed “second metal features”, Huang states,
FIGS. 30A-C illustrate an alternative configuration where the dummy features 142 include both dummy conductive lines and dummy conductive vias that are disposed in both the backside interconnect structure 136 and the front-side interconnect structure 120.
(Huang: ¶ 93; emphasis added)
The dummy features 142 are thermally connected to the active devices of the device layer 115 and/or the conductive lines 134 (e.g., a power rail). The dummy features 142, however, may be electrically isolated from all active devices in the device layer 115 and/or the conductive lines 134 in the semiconductor die.
(Huang: ¶ 88; emphasis added)
The dummy features 142 may be inserted into previously unoccupied areas of the backside interconnect structure 136 and/or the front-side interconnect structure 140 [sic; should be 120]. Accordingly, the layout of functional elements of the semiconductor die (e.g., signal lines, power lines, passive devices, and the like) are unaffected by the inclusion of the dummy features 142.
(Huang: ¶ 93; emphasis added)
This is all of the limitations of claim 11.
With regard to claim 12, Huang further discloses,
12. (Original) The IC structure of claim 11,
[1] wherein the first metal features 122 include electrical metal lines and electrical vias [¶ 71], and the electrical vias are vertically disposed between the electrical metal lines [as shown in Figs. 30A-30C],
[2] wherein the second metal features 142 include thermal vias [taken to be the structure forming the entire thermal path 147 (Fig. 30C; ¶ 94; infra)], and
[3] each of the thermal vias have a greater height in a vertical direction than at least a height of an electrical via 122 plus a height of an electrical metal line 122 [as shown in Fig. 30C].
Huang states,
The dummy features 142 in the interconnect structure 120 may provide a thermal dissipation path from the device layer 115 through the interconnect structure 120 as indicated by arrow 147.
(Huang: ¶ 94; emphasis added)
… an arrow 145 indicates a thermal dissipation path …
(Huang: ¶ 87; emphasis added)
VII. Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1-3, 6, 8, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of US 2014/0131860 (“Kanda”).
Claim 16 reads,
16. (Original) The IC structure of claim 11, further comprising:
[1] a backside interconnect structure on a back side of the device layer,
[2a] wherein the backside interconnect structure includes third metal features and fourth metal features embedded in a backside IMD layer,
[2b] the third and fourth metal features are isolated from each other by the backside IMD layer,
[2c] the third metal features are electrically connected to an S/D region or a gate stack of the transistor devices, and
[2d] the fourth metal features are electrically isolated from the transistor devices; and
[3] a heat spreader layer on a back side of the backside interconnect structure,
[4] wherein the heat spreader layer is made of a heat spreader material that is thermally conductive and electrically insulating,
[5] wherein the fourth metal features directly contacts the heat spreader layer.
The prior art of Huang, as explained above, discloses each of the features of claim 11.
With regard to claims 16, Huang further discloses,
16. (Original) The IC structure of claim 11, further comprising:
[1] a backside interconnect structure 136 on a back side of the device layer 115,
[2a] wherein the backside interconnect structure 136 includes third metal features 134, 140 and fourth 142/146/148 metal features embedded in a backside IMD layer 126, 132, 138 [¶¶ 85-88],
[2b] the third 140 and fourth 142/146/148 metal features are isolated from each other by the backside IMD layer,
[2c] the third metal features 134 are electrically connected to an S/D region 90/92 or a gate stack of the transistor devices [as shown in Figs. 30B-30C], and
[2d] the fourth metal features 142 are electrically isolated from the transistor devices [as shown by the dummy thermal via 142 in the dashed box plus dummy UBM 146 and dummy solder ball 148 (¶ 91) and ¶ 88 (supra)]; and
[3]-[5] … [not taught] …
With regard to features [3]-[5] of claim 16, Huang does not disclose a heat spreader.
Kanda, like Huang, teaches a semiconductor device including electrically active interconnect 24s-28s, 24S-28S, 24d-28d, 24D-28D (Kanda: Fig. 1; ¶ 34) and electrically-isolated heat dissipation structures 20H in a “heat dissipation region 21B” made by stacked metal lines 24H-28H physically connected by vias 24h-28h (Kanda: Figs. 1, 11A-11C, 12, 13; ¶ 37). Kanda also show that the metal lines 24H-28H and vias 24h-28h may be replaced by a “single metal pillar” 20H1 (Kanda: Fig. 6; ¶ 56). Also like Huang, Kanda teaches that each thermal via 20H, 20H1 includes a solder ball 30H. The solder balls 30H directly contacts and connects the thermal vias 20H, 20H1 to a heat sink 11H of a printed wiring board 11. In this regard, Kanda states, “Here, the conductor pattern 11H and the wiring board 11 function as a heatsink that conducts heat generated at the transistor 11Tr through the semiconductor chip 21, the heat dissipation structure 20H, the solder bump 30H, and the conductor pattern 11H on the wiring board 11.” (Kanda: ¶ 39; emphasis added)
Inasmuch as the purpose of the solder balls 148 in Huang are for electrical connection to a wiring board, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to attached the heat spreader layer 11H/11 directly to the dummy solder ball 148 of the dummy thermal via 142/146/148 of the backside interconnect 136 in order to (1) electrically connect the semiconductor device to a wiring board and (2) provide a heat sink for the desired thermal dissipation.
So modified, Huang/Kanda teaches features [3]-[5] of claim 16, as follows:
[3] a heat spreader layer [of Kanda 11H/11] on a back side of the backside interconnect structure [136 of Huang],
[4] wherein the heat spreader layer 11H/11 is made of a heat spreader material [conductor pattern] that is thermally conductive [i.e. conductor pattern 11H and electrically insulating [i.e. the insulating portion of the wiring board 11],
[5] wherein the fourth metal features [142/146/148 of Huang] directly contacts the heat spreader layer 11H/11 [as shown in Figs. 1 and 6 of Kanda].
This is all of the limitations of claim 6.
Claim 1 reads,
1. (Original) An integrated circuit (IC) structure, comprising:
[1a] a device layer having transistor devices,
[1b] the transistor devices having channel regions between source/drain (S/D) regions and gate stacks over the channel regions;
[2a] a frontside interconnect structure on a front side of the device layer, wherein
[2b] the frontside interconnect structure includes first metal features and second metal features embedded in an intermetal dielectric (IMD) layer,
[2c] the first and second metal features are isolated from each other by the IMD layer,
[2d] the first metal features are electrically connected to an S/D region or a gate stack of the transistor devices, and
[2e] the second metal features are electrically isolated from the transistor devices;
[3a] a backside interconnect structure on a back side of the device layer, wherein
[3b] the backside interconnect structure includes third metal features and fourth metal features embedded in a backside IMD layer,
[3c] the third and fourth metal features are isolated from each other by the backside IMD layer,
[3d] the third metal features are electrically connected to an S/D region or a gate stack of the transistor devices, and
[3e] the fourth metal features are electrically isolated from the transistor devices; and
[4a] a heat spreader layer on a back side of the backside interconnect structure,
[4b] wherein the heat spreader layer is made of a heat spreader material that is thermally conductive and electrically insulating.
Each of the limitations of claim 1 have been addressed by the combination of Huang with Kanda for the heat spreader, for the reasons explained under the rejection of claim 11 over Huang, alone, and Huang in view of Kanda for claim 16.
With regard to claim 2, Huang further discloses,
2. (Original) The IC structure of claim 1,
[1] wherein the first and the third metal features include electrical metal lines and electrical vias, and the electrical vias are vertically disposed between the electrical metal lines,
[2] wherein the second and the fourth metal features include thermal vias, and each of the thermal vias have a greater height in a vertical direction than each of the electrical vias.
See discussion under claim 11, above.
Claim 3 reads,
3. (Original) The IC structure of claim 2, wherein
[1] the electrical metal lines extend beyond a side surface of the electrical vias along a first direction or along a second direction perpendicular to the first direction, and
[2] the thermal vias are metal pillars having vertical side surfaces without extensions beyond the vertical side surfaces.
With regard to claim 3 Huang further discloses,
3. (Original) The IC structure of claim 2, wherein
[1] the electrical metal lines [lines of 122] extend beyond a side surface of the electrical vias [vias of 122] along a first direction or along a second direction perpendicular to the first direction [i.e. in length and width of the lines], and
[2] … [not taught] …
Huang does not teach feature [2] of claim 3.
As explained above, under claim 16, Kanda also teaches that the metal lines 24H-28H and vias 24h-28h may be replaced by a “single metal pillar” 20H1 (Kanda: Fig. 6; ¶ 56).
[2] the thermal vias 142/146/148 are metal pillars having vertical side surfaces without extensions beyond the vertical side surfaces.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to replace the thermal via 142 with a single metal pillar, because Kanda teaches that each of lines plus vias 20H (Fig. 1) and single metal pillars 20H1 (Fig. 6) are suitable alternatives for the identical purpose of heat dissipation. (See MPEP 2143.) As such, the use of a single metal pillar is a matter of design choice, as evidenced by Kanda.
This is all of the limitations of claim 3.
Claim 6 reads,
6. (Original) The IC structure of claim 1, wherein the fourth metal features span from the device layer to the heat spreader layer and the fourth metal features land on a top surface of the heat spreader layer.
The embodiment in Figs. 30C does not show that the dummy thermal via 142/146/148 in the backside interconnect 136 extends all of the way therethrough to contact the device layer 115. However, Huang shows that the dummy thermal via 142 in the front-side interconnect 120 extends all of the way therethrough to contact both the device layer 115 and the bonding oxide layer 152.
Kanda further teaches that the thermal vias 20H (Fig. 1), 20H1 (Fig. 6) extend all of the way through the interconnect layer.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include dummy thermal vias 142 extending all of the way though the backside interconnect 136, such as shown in the front-side interconnect 120, in order to provide a thermal path from the device layer 115 to the heat spreader 11H/11 of Huang/Kanda.
This is all of the limitations of claim 6.
With regard to claim 8, Kanda further discloses,
8. (Original) The IC structure of claim 1, wherein the heat spreader material has a thermal conductivity between about 10 and about 500 W/m/K.
In is held, absent evidence to the contrary, the metal used in the conductive pattern 11H of Kanda inherently has a thermal conductivity between about 10 and about 500 W/m/K. As such, the burden of proof is shifted to Applicant to prove the contrary. (See MPEP 2112(I)-(V).)
Claim 17 reads,
17. (Currently amended) An integrated circuit (IC) structure, comprising:
[1a] transistor devices in a device layer over a device substrate,
[1b] each transistor device having a channel region between source/drain (S/D) regions and a gate stack over the channel region;
[2] device-level contacts over and electrically coupled to the S/D regions and the gate stack of the transistor devices;
[3a] a frontside interconnect structure over the device-level contacts, the frontside interconnect structure having
[3b] electrical metal lines,
[3c] electrical vias coupled vertically between the electrical metal lines, and
[3d] thermal vias electrically isolated from the electrical metal lines and vias;
[4] a carrier substrate bonded to a top surface of the frontside interconnect structure;
[5a] a backside interconnect structure on a back side of the device layer, the backside interconnect structure having
[5b] backside electrical metal lines,
[5c] backside electrical vias coupled vertically between the backside electrical metal lines, and
[5d] backside thermal vias electrically isolated from the backside electrical metal lines and vias; and
[6a] a heat spreader layer on a back surface of the backside interconnect structure,
[6b] the heat spreader layer is made of a heat spreader material that is thermally conductive and electrically insulating.
Each of the limitations of claim 17 have been addressed by the combination of Huang with Kanda for the heat spreader, for the reasons explained under the rejection of claim 11 over Huang, alone, and Huang in view of Kanda for claim 16.
C. Claims 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Kanda, as applied to claims 1 and 17, above, and further in view of US 2001/0017373 (“Nishibayashi”).
Claims 9 and 20 read,
9. (Original) The IC structure of claim 1, wherein the heat spreader material includes diamond, AlN, BN, Al2O3, BeO, or a combination thereof.
20. (Currently amended) The IC structure of claim 17, wherein the heat spreader layer includes diamond, AlN, BN, Al2O3, BeO, or a combination thereof.
The prior art of Huang in view of Kanda, as explained above, teaches each of the features of claims 1 and 17.
Kanda does not teach what the non-conductive materials of the wiring board 11 functioning as a heat spreader 11H/11 includes, and does not therefore teach “one of diamond, AlN, BN, Al2O3, BeO.”
Nishibayashi teaches (1) a wiring board made of conductive patterns in/on diamond at least in order to improved heat dissipation (¶¶ 2, 4, 8). Nishibayashi also teaches that wiring boards made of conductive patterns in/on each of AlN, Al2O3, and BeO are known (¶ 6).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include any of diamond, AlN, Al2O3, and BeO as the non-conductive material of the wiring board 11 of Kanda, that is used in Huang, in order to improve the thermal conductivity and consequently the heat dissipation capacity of the wiring board, as taught by Nishibayashi. As such, Nishibayashi may be seen as an improvement to Kanda in this aspect. (See MPEP 2143.)
This is all of the limitations of claim 9 and 20.
VIII. Allowable Subject Matter
Claims 4, 5, 7, 10, 13-15, and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 4 reads,
4. (Original) The IC structure of claim 1,
[1] wherein the second and the fourth metal features are first thermal vias completely surrounded by and directly contacting dielectric materials, further comprising:
[2a] second thermal vias embedded in the IMD layer, wherein
[2b] each of the second thermal vias includes a metal portion and a thermal insulating portion,
[2c] the thermal insulating portions of the second thermal vias directly land on the first metal features, and
[2d] the thermal insulating portions of the second thermal vias separate the first metal features from the metal portions of the second thermal vias; and
[3a] third thermal vias embedded in the backside IMD layer, wherein
[3b] each of the third thermal vias includes a metal portion and a thermal insulating portion,
[3c] the thermal insulating portions of the third thermal vias directly land on the third metal features, and
[3d] the thermal insulating portions of the third thermal vias separate the third metal features from the metal portions of the third thermal vias.
With regard to claim 4, Huang teaches (1) that there may be a plurality of dummy thermal metal vias 142 on the front side and back side of the device layer 115, as explained under claims 11 and 16, thereby teaching the second and third thermal vias of features [2a] and [3a] of claim 4 and (2) the dummy materials include both metal materials and electrically insulating materials, aluminum oxide and aluminum nitride (Huang: ¶ 89), which are thermally insulating within the meaning of the Instant Application as evidenced by at least claim 5, which includes aluminum oxide and aluminum nitride as thermally insulating materials, thereby rendering features [2c] and [3c] obvious. Huang also teaches that the dummy via 142 on the back side in each of Fig. 29B is in contact with the power rail 134, which may be the thermally insulating portion that may be AlN or Al2O3 in order to prevent electrical contact between the contacting metal lines 140 with the power rail 134, thereby rendering feature [3c] and [3d] obvious.
It is not clear that feature [2c] of claim 4 is taught since there are no power rails on the front side of the device layer 115 and the dummy thermal vias 142 contact the source/drain regions of the gate stack, which are not the claimed “first metal features”. Thus, the prior art does not reasonably teach or suggest—in the context of claim 4—the following limitations:
[2c] the thermal insulating portions of the second thermal vias directly land on the first metal features, and
[2d] the thermal insulating portions of the second thermal vias separate the first metal features from the metal portions of the second thermal vias; and
Claim 5 would be allowable at least for including the same allowable limitation by depending from claim 4.
Claims 7 and 18 read,
7. (Original) The IC structure of claim 1, further comprising:
[1a] a redistribution layer (RDL) structure on a back side of the heat spreader layer,
[1b] the RDL structure includes aluminum pads embedded in a passivation layer,
[2] wherein the heat spreader layer embeds a through via that electrically connects the third metal features to the aluminum pads.
18. (Currently amended) The IC structure of claim 17, further comprising:
[1] a redistribution layer (RDL) structure on a back surface of the heat spreader layer,
[2] wherein the RDL structure includes aluminum bonding pads embedded in a passivation layer.
The prior art does not reasonably teach or suggest—in the context of each of claims 7 and 18—an RDL on the back side of the heat spreader. The heat spreader of Kanda, used in Huang, is a wiring board 11H/11 which would not reasonably include an RDL on the back side.
Claim 19 would be allowable at least for including the same allowable limitation by depending from claim 18.
Claim 10 reads,
10. (Original) The IC structure of claim 1, wherein
[1] the transistor devices include high power devices and low power devices, and
[2] the second and the fourth metal features are concentrated laterally closer to the high power devices than the low power devices.
The prior art does not reasonably teach or suggest—in the context of claim 10—transistor devices including both high-power and low-power.
With regard to claim 13, Huang discloses,
13. (Original) The IC structure of claim 11,
[1] wherein the second metal features 142 are floating thermal vias completely surrounded by and directly contacting dielectric materials, further comprising:
[2a] non-floating thermal vias 142 embedded in the IMD layer [Fig. 30C], wherein
[2b] each of the non-floating thermal vias 142 includes a metal portion and a thermal insulating portion [¶ 89],
[2c] the thermal insulating portion directly lands on the first metal features, and
[2d] the thermal insulating portion separates the first metal features from the metal portion.
Claim 13 includes allowable subject matter for the same reason as claim 4.
Claim 14 and 15 would be allowable at least for including the same allowable limitation by depending from claim 13.
IX. Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 5,625,232 (“Numata”) is cited for disclosing thermal vias 122/134 including metal portions 122 and thermally insulating portions 134 (paragraph bridging cols 10-11), wherein the thermally insulating portion 134 lands on and separates the metal portion from an active metal line 114. See Figs. 3A-3C, 4 and the associated text.
US 2022/0130761 (“Kim”) is cited for teaches a semiconductor device layer CEL having frontside WIL and backside PDN interconnect structures including thermal vias to dissipate heat. See Fig. 12 and associated text.
US 2017/0213821 (“Or-Bach”) is cited for disclosing at least all of the limitations of claim 11, noting at least the thermal vias 444, 445, 446, 447 (Fig. 4; ¶ 65) and 1414 (Fig. 14D; ¶ 143) in the frontside interconnect structures.
Conclusion
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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