DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 7 of U.S. Patent No. 11916070 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because
Regarding claim 1, claim 1 of US 11916070 B2 teaches a method of making a semiconductor device, comprising:
recessing a surface in a second surface region of a semiconductor substrate relative to a top surface of a first surface region of the semiconductor substrate by a first recess distance DR (column 23 lines 66 to column 24 lines 12 of claim 1 of US 11916070 B2);
depositing a first layer of a first material on the top surface of the first surface region and the recessed surface of the second surface region (column 24 lines 13-15 of claim 1 of US 11916070 B2);
depositing a first layer of a second material on the first layer of the first material (column 24 lines 16-18 of claim 1 of US 11916070 B2);
removing a first portion of the layers of the first and second materials from over the first surface region while retaining a second portion of the first layers of the first and second materials over the second surface region (column 24 lines 19-22 of claim 1 of US 11916070 B2);
depositing a second layer of the first material and a second layer of the second material over both the first surface region and the second portion of the first layers of the first and second materials over the second surface region (column 24 lines 23-28 of claim 1 of US 11916070 B2); and
patterning and etching second layers of the first and second materials and the second portion of the first layers of the first and second materials to form a first stack having a first stack height H1 over the first surface region and a second stack having a second stack height H2 over the second surface region, wherein the first and second stack heights H1 and H2 satisfy a relationship H2 > H1 (column 24 lines 29-34 of claim 1 of US 11916070 B2).
Regarding claim 10, claim 7 of US 11916070 teaches a method of making a semiconductor device, comprising:
defining a plurality of functional blocks on a semiconductor substrate (column 24 lines 62-63 of claim 7 of US 11916070 B2);
grouping the plurality of functional blocks into a plurality of subsets of functional blocks (column 24 lines 66-67 and column 25 lines 1-3 of claim 7 of US 11916070 B2);
determining a plurality of performance targets for each of the plurality of subsets of functional blocks (column 24 lines 64-65 of claim 7 of US 11916070 B2);
identifying a plurality of nanosheet stack configurations satisfying each of the plurality performance targets (column 24 lines 62-63 of claim 7 of US 11916070 B2); and
forming the nanosheet stack configurations on a plurality of portions of the semiconductor substrate corresponding to each subset of functional blocks (column 25 lines 1-3 of claim 7 of US 11916070 B2), wherein forming the nanosheet stack configurations comprises:
forming first nanosheet configurations having a height H1 corresponding to first subset of functional blocks on a plurality of first portions of the semiconductor substrate; and forming second nanosheet configurations having a height H2 corresponding to a second subset of functional blocks on a plurality of second portions of the semiconductor substrate, wherein H1 and H2 satisfy a relationship H2 > H1 (column 25 lines 5-41 of claim 7 of US 11916070 B2).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 17 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. (US 2011/0031473 A1).
Regarding claim 17, Chang teaches a method (Figs. 6-21D of Chang) of making a semiconductor device (SRAM cell 100 in Fig. 1 of Chang), comprising:
defining a plurality of functional blocks (as written, the term “defining” does not require any physical step but merely identifying. An identification of regions the substrate 602 intended for the NFETs and PFETs in Fig. 1 meets the requirement of this step. This step is implicit in the method of Chang) on a semiconductor substrate (SOI substrate 602 in Fig. 6);
selecting a nanosheet stack configuration from a plurality of nanosheet stack configurations for achieving a target performance for each of the functional blocks (the choice of layers 604-614 in Fig. 6 of Chang); and
forming each of the selected nanosheet stack configurations (as shown in Figs. 7A-7C, the stacks 702 are patterned and separated by the STI 706) on a portion (upper portion of the substrate 602) of the semiconductor substrate corresponding to each of the plurality of functional blocks, wherein forming the selected nanosheet stack configurations further comprises:
forming a plurality of first nanosheet stack configurations (the configurations of the stacks of transistors 102, 104 in Fig. 1) having a height H1 (height of NFET layers as shown in Fig. 1) corresponding to first functional block (the regions of the transistors 102-104) on a first portion of the semiconductor substrate; and
forming a plurality of second nanosheet stack configurations (the configurations of the stacks of transistors 106, 108 in Fig. 1) having a height H2 (height of the nanowire channel layers 106/108) corresponding to a second functional block on a second portion of the semiconductor substrate, wherein H1 and H2 satisfy a relationship H2 > H1 (as shown in Fig. 1, the height of the nanowire channel stacks of 106-108 is greater than that of 102-104).
Claims 10-11, 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawa et al. (US 2015/0370951 A1).
Regarding claim 10, Kawa teaches a method (Figs. 3A-3B of Kawa) of making a semiconductor device, comprising:
defining a plurality of functional blocks (as written, the term “defining” does not require any physical step but merely identifying. An identification of regions for the stacks 321-323 and 231-233 on the substrate Fig. 3A-3B meets the requirement of this step. This step is implicit in the method of Kawa) on a semiconductor substrate;
grouping the plurality of functional blocks into a plurality of subsets (320 and 230 can be identified as subsets in Fig. 3A) of functional blocks;
determining a plurality of performance targets (these stacks are intended for forming PMOS/NMOS transistors) for each of the plurality of subsets of functional blocks;
identifying a plurality of nanosheet stack configurations (the determination of configurations include parameters such as material choice, impurity concentration, dopant, dimensions… of the nanowire in each stack are implicit steps in the method of making the device in Fig. 3A-3B) satisfying each of the plurality performance targets; and
forming the nanosheet stack configurations on a plurality of portions (each portion is a region of the substrate for each of the stacks 321-323, 231-233 in Fig. 3B) of the semiconductor substrate corresponding to each subset of functional blocks (as defined), wherein forming the nanosheet stack configurations comprises:
forming first nanosheet configurations (configurations of the stacks 321-323 in Fig. 3A-3B) having a height H1 (height of the stacks 321-323) corresponding to first subset (320) of functional blocks on a plurality of first portions of the semiconductor substrate; and
forming second nanosheet configurations (the configurations of the stacks 231-233) having a height H2 (height of the stacks 231-233) corresponding to a second subset (230) of functional blocks on a plurality of second portions of the semiconductor substrate, wherein H1 and H2 satisfy a relationship H2 > H1 (as shown in Fig. 3B of Kawa).
Regarding claim 11, Kawa teaches all limitations of the method according to claim 10, and further comprising: removing an upper portion of the semiconductor substrate in the plurality of second portions of the semiconductor substrate to form a plurality of recessed substrate surface regions (recess between the stacks of nanowires in Fig. 3A-3B of Kawa).
Regarding claim 16, Kawa teaches all limitations of the method according to claim 10, and further comprising: forming an isolation structure (260 in Fig. 3B of Kawa) separating the first nanosheet configurations from the second nanosheet configurations.
Regarding claim 17, Kawa teaches a method (Figs. 3A-3B of Kawa) of making a semiconductor device (device in Fig. 3A-3B of Kawa), comprising:
defining a plurality of functional blocks (as written, the term “defining” does not require any physical step but merely identifying. An identification of blocks 230 and 320 the substrate intended for the PMOS and NMOS in Fig. 3A-3B meets the requirement of this step. This step is implicit in the method of Kawa) on a semiconductor substrate (SOI substrate 270 in Fig. 3A-3B);
selecting a nanosheet stack configuration from a plurality of nanosheet stack configurations for achieving a target performance for each of the functional blocks (the action “selecting” is also implicit with the decision of selecting which areas of substrate to form the PMOS-NMOS in Fig. 3A-3B of Kawa); and
forming each of the selected nanosheet stack configurations (stacks 231-233 and 321-323 in Fig. 3A-3B) on a portion (portion of the substrate for the blocks 230-320 of Fig. 3A) of the semiconductor substrate corresponding to each of the plurality of functional blocks, wherein forming the selected nanosheet stack configurations further comprises:
forming a plurality of first nanosheet stack configurations (the configurations of the stacks 321-323) having a height H1 (height of the stacks 321-323) corresponding to first functional block (230) on a first portion (area of substrate for block 320) of the semiconductor substrate; and
forming a plurality of second nanosheet stack configurations (the configurations of the stacks 231-233) having a height H2 (height of the stacks 231-233) corresponding to a second functional block on a second portion (area of substrate for block 230) of the semiconductor substrate, wherein H1 and H2 satisfy a relationship H2 > H1 (as shown in Fig. 3B of Kawa).
Regarding claim 18, Kawa teaches all limitations of the method according to claim 17, and further comprising:
adjusting the first nanosheet stack configurations to form a first subset (first subset is a group of the top 3 nanowires in the stack 321 in Fig. 3B of Kawa) of the plurality of first nanosheet stack configurations having a first area A1 (interface area of the top 3 nanowires in the stack 321) and a second subset (bottom nanowire in the stack 321) of the plurality of first nanosheet stack configurations having a second area A2, wherein the first and second areas satisfy a relationship A1 > A2 (this follows the definitions of first and second area above).
Regarding claim 19, Kawa teaches all limitations of the method according to claim 17, and further comprising: adjusting the first nanosheet stack configurations to form a plurality of first nanosheet stack configurations having a first area A1 (interface area of the top 3 nanowires in the stack 321); and adjusting the second nanosheet configurations to form a plurality of second nanosheet stacks configurations having a second area A2 (interface area of the top 2 nanowires in the stack 231); wherein the first and second areas satisfy a relationship A1 > A2 (this follows the definitions of first and second area above).
Regarding claim 20, Kawa teaches all limitations of the method according to claim 17, and further comprising:
selecting the first nanosheet stack configuration to comprise N nanosheets (321 in Fig. 3B of Kawa has 4 nanosheets); and
selecting the second nanosheet stack configuration to comprise M nanosheets (231 in Fig. 3B of Kawa has 6 nanosheets), wherein N and M are both integers having values of at least 2 and further wherein N ≠ M (as defined above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kawa as applied to claim 10 above, and further in view of Leobandung et al. (US 2015/0069328 A1).
Regarding claim 13, Kawa teaches all limitations of the method according to claim 10, and further comprising:
forming a first plurality of N alternating layers of a first material and a second material (the stack of alternating layers up to the top nanowires of stacks 321-323 in Fig. 3B is described in [0035] of Kawa) over the plurality of first portions of the semiconductor substrate;
forming a second plurality of M alternating layers of the first material and the second material over the plurality of second portions of the semiconductor substrate, wherein N ≠ M (the stack of alternating layers up to the top nanowires of stacks 231-233 in Fig. 3B is described in [0035] of Kawa); and
But Kawa does not teach the method comprising: etching the first and second pluralities of alternating layers to form the first and second nanosheet configurations.
Leobandung teaches a method of forming nanowire device which comprising of: forming a stack of alternating layers (Fig. 2 of Leobandung); patterning the stack to form fin structures of alternating layers (Fig. 3 of Leobandung); etching the sacrificial layers to release the nanowire channel layers (Fig. 20 of Leobandung).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have used Leobandung’s method since this is a typical method of forming nanowire channels.
Regarding claim 14, Kawa in view of Leobandung teaches all limitations of the method according to claim 13, and further comprising: removing the layers of the first material from the first and second nanosheet configurations (as combined with Leobandung above).
Regarding claim 15, Kawa teaches all limitations of the method according to claim 10, but does not teach further comprising: forming a first epitaxial structure between adjacent first nanosheet configurations; and forming a second epitaxial structure between adjacent second nanosheet configurations.
Leobandung teaches a method of forming nanowire device. The method comprises: forming epitaxial source/drain structures (136 in Fig. 27) adjacent the nanowire channels (108, 112) in order to improve the device’s performance (exerting stress/strain on the carriers in the channel).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the epitaxial source/drain structures as according to Leobandung in order to improve the device performance.
Allowable Subject Matter
Claims 1-9 are allowed.
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, the prior art of record does not disclose or fairly suggest a method of making a semiconductor device, comprising: “recessing a surface in a second surface region of a semiconductor substrate relative to a top surface of a first surface region of the semiconductor substrate by a first recess distance DR; depositing a first layer of a first material on the top surface of the first surface region and the recessed surface of the second surface region; depositing a first layer of a second material on the first layer of the first material; removing a first portion of the layers of the first and second materials from over the first surface region while retaining a second portion of the first layers of the first and second materials over the second surface region; depositing a second layer of the first material and a second layer of the second material over both the first surface region and the second portion of the first layers of the first and second materials over the second surface region; and patterning and etching second layers of the first and second materials and the second portion of the first layers of the first and second materials to form a first stack having a first stack height H1 over the first surface region and a second stack having a second stack height H2 over the second surface region, wherein the first and second stack heights H1 and H2 satisfy a relationship H2 > H1”.
Regarding claim 12, the prior art of record does not disclose or fairly suggest a the method comprising: “removing an upper portion of the semiconductor substrate in the plurality of second portions of the semiconductor substrate to form a plurality of recessed substrate surface regions, wherein the recessed substrate surface regions are recessed by a first recess distance DR, and wherein the first recess distance DR satisfies a relationship DR = H2 - H1” along with other limitations of claim 10.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Tuan A Hoang/ Primary Examiner, Art Unit 2898
Prosecution Insights