DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment filed on 9/2/2026 is acknowledged. Claims 10-12, 17 have been amended.
Response to Arguments
Applicant’s arguments with respect to claims 10-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Noh et al. (US 2020/0006333 A1).
Regarding claim 17, Noh teaches a method of making a semiconductor device (Figs. 4-24 illustrate the method of forming the device in Figs. 1-3), comprising:
defining a plurality of functional blocks (transistors in regions I, II as shown in Fig. 3) on a semiconductor substrate (100);
selecting a nanosheet stack (stack shown in Fig. 5) configuration from a plurality of nanosheet stack configurations (different choices for materials, fin dimensions… for layers 110 and 120 in Fig. 5; these choices and dimensions are always present for any devices and are necessary considerations that a practitioner must decide when make a device) for achieving a target performance (target performance of these devices are also implicit aspect of making a device) for each of the functional blocks; and
forming each (each of nanowire stacks in Fig. 7) of the selected nanosheet stack configurations on a portion of the semiconductor substrate corresponding to each of the plurality of functional blocks,
wherein forming the selected nanosheet stack configurations further comprises:
forming a plurality of first nanosheet stack configurations (nanowire stacks in region I) having a height H1 (height of top surface of the base fin 102 in region I in Fig. 14) corresponding to first functional block on a first portion (region I) of the semiconductor substrate; and
forming a plurality of second nanosheet stack configurations (nanowire stacks in region I) having a height H2 (height of top surface of the lowest layer 124 in region II) corresponding to a second functional block on a second portion (region II) of the semiconductor substrate, wherein H1 and H2 satisfy a relationship H2 > H1 (as shown in Fig. 14, H2 is greater than H1),
wherein upper surfaces (top surfaces of topmost nanowire 122 and topmost nanowire 124 in Fig. 14) of the plurality of first nanosheet stack configurations and upper surfaces of the plurality of second nanosheet stack configurations lie substantially in a common horizontal plane (as shown in Fig. 14 of Noh).
Regarding claim 18, Noh teaches all limitations of the method according to claim 17, and further comprising:
adjusting the first nanosheet stack configurations to form a first subset (subset of nanowires 126 in Fig. 23 of Noh is formed by removing the sacrificial patterns 116) of the plurality of first nanosheet stack configurations having a first area A1 (total area of exposed nanowires 126 in Fig. 23) and a second subset (subset of nanowires covered by the isolation 162, which is the base fin 102) of the plurality of first nanosheet stack configurations having a second area A2 (area of the top surface of base fin 102 in Fig. 24), wherein the first and second areas satisfy a relationship A1 > A2 (the base fin 102 only has the top surface exposed).
Regarding claim 19, Noh teaches all limitations of the method according to claim 17, and further comprising:
adjusting the first nanosheet stack configurations to form a plurality of first nanosheet stack configurations (subset of nanowires 126 in Fig. 23 of Noh is formed by removing the sacrificial patterns 116) having a first area A1 (total area of exposed nanowires 126 in Fig. 24); and
adjusting the second nanosheet configurations to form a plurality of second nanosheet stacks configurations having a second area A2 (removing the sacrificial layers 118 to expose surfaces of nanowires 128 as shown in Fig. 23-24);
wherein the first and second areas satisfy a relationship A1> A2 (as shown in Fig. 24 of Noh).
Regarding claim 20, Noh teaches all limitations of the method according to claim 17, and further comprising: selecting the first nanosheet stack configuration to comprise N nanosheets (number of exposed nanosheets 126 in Fig. 24 of Noh); and selecting the second nanosheet stack configuration to comprise M nanosheets (number of exposed nanosheets 128 in Fig. 24 of Noh), wherein N and M are both integers having values of at least 2 and further wherein N # M (as shown in Fig. 24 of Noh).
Allowable Subject Matter
Claims 1-17 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, the prior art of record does not disclose or fairly suggest a method of making a semiconductor device, comprising: “recessing a surface in a second surface region of a semiconductor substrate relative to a top surface of a first surface region of the semiconductor substrate by a first recess distance DR; depositing a first layer of a first material on the top surface of the first surface region and the recessed surface of the second surface region; depositing a first layer of a second material on the first layer of the first material; removing a first portion of the layers of the first and second materials from over the first surface region while retaining a second portion of the first layers of the first and second materials over the second surface region; depositing a second layer of the first material and a second layer of the second material over both the first surface region and the second portion of the first layers of the first and second materials over the second surface region; and patterning and etching second layers of the first and second materials and the second portion of the first layers of the first and second materials to form a first stack having a first stack height H1 over the first surface region and a second stack having a second stack height H2 over the second surface region, wherein the first and second stack heights H1 and H2 satisfy a relationship H2 > H1”.
Regarding claim 10, the prior art of record does not disclose or fairly suggest a method of making a semiconductor device, comprising: “forming the nanosheet stack configurations on a plurality of portions of the semiconductor substrate corresponding to each subset of functional blocks, wherein forming the nanosheet stack configurations comprises: forming first nanosheet configurations having a height H1 corresponding to first subset of functional blocks on a plurality of first portions of the semiconductor substrate; and forming second nanosheet configurations having a height H2 corresponding to a second subset of functional blocks on a plurality of second portions of the semiconductor substrate, wherein H1 and H2 satisfy a relationship H2 > H1; and removing an upper portion of the semiconductor substrate in the plurality of second portions of the semiconductor substrate to form a plurality of recessed substrate surface regions, wherein the recessed substrate surface regions are recessed by a first recess distance DR, and wherein the first recess distance DR satisfies a relationship DR = H2 - H1” along with other limitations of the claim.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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