DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nicolas L. Breil et al (U. S. Patent Application: 2024/0014076 here after 076), further in
view of Jiyeon Kim (U. S. Patent Application: 2024/0218505, here after 505), and S. Jeon et al (U. S. Patent Application: 2025/0199396, here after 396).
Claim 1 is rejected. 076 teaches a method (for making a semiconductor device)
comprising: depositing a contact capping layer (520) over inner surfaces of a cavity
(516) of a semiconductor substrate comprising a dielectric material (510) [fig. 5F, 0072],
the inner surfaces comprising a surface of a contact structure (518) within the cavity [fig. 5D], sidewall of the cavity [fig. 5D], and a bottom surface of the cavity [fig. 5F], wherein the contact capping layer (520) comprising molybdenum silicide or ruthenium silicide and deposited by CVD [0073-0074]. 076 further teaches depositing a metal cap (522) selectively on a surface of the contact capping layer (520) within the cavity [fig. 5H, 0079], which in fact can act as a seeding layer on surface of capping layer for next layer (524). 076 does not teach the detail of deposition process. 505 teaches a method of making metal silicide for semiconductor devices by CVD or ALD [step 104 fig. 1, 0035], where the silicide layer (molybdenum) is made by (repeating steps 108 and 110) [0038];
(a) flowing hydrogen (H2) gas [0040] into a processing chamber for a first period
of time;
(b) delivering a (molybdenum) precursor for a second period of time and halting
the delivery of the (Mo) precursor for a third period of time [0040, 0046], wherein the
second period of time and the third period of time overlap with the first period of time
(hydrogen, inert gas and inert gas flow together for a time duration and also teaches
purging by inert gas between a precursor pulse and reactant pulse based on 0028,
therefore by flowing hydrogen, inert gas, and Mo precursor, t1 and t2 overlaps, and
during stopping flowing molybdenum precursor and purge or halting step and removing
molybdenum precursor, the inert gas still flows as purge gas for t3n therefore t1, t2, and
t3 overlaps; 505 also teaches;
(c) delivering a silicon containing gas into the processing chamber for a fourth
period of time [0047] and halting the delivery for a fifth period of time [0028], wherein the
second period of time, and the fourth period of time do not overlap (505 teaches purge
steps between precursor flowing and reactant flowing therefore do not overlaps); and (d) repeating (a), (b), and (c) one or more times [fig. 1, 0038]. Therefore, it would
have been obvious to one of ordinary skill in the art at the time of the invention was
made to have a method of making semiconductor device as 076 teaches, where the
metal silicide layer is made by method of 505, because it teaches suitable method for
depositing metal (Mo)silicide for making semiconductive devices. 505 teaches following carrier gas (inert gas) and molybdenum precursor gas together, but does not clearly teach flowing silicon precursor and carrier (inert gas). However, it is known in the art to have precursor gas and reactant gas flow in chamber with a carrier gas (inert gas) in atomic layer deposition process. For example, 396 teaches forming a metal silicide (MoSi) with ALD where the molybdenum precursor and silicon precursor flow the chamber by carrier (inert gas) [ 0057-0058, 0072]. Therefore, it would
have been obvious to one of ordinary skill in the art at the time of the invention was
made to have a method of making semiconductor device as 076, and 505 teach, where silicon precursor also introduces to chamber with carrier(inert) gas, because it is suitable way to introduce reactant gas to ALD chamber. Therefore, when inert gas flows for purging molybdenum precursor, halting time (third period), silicon containing gas added to the inert gas and delivering time (fourth period) happens during it.
Claims 2 and 17 are rejected as 076 further teaches the metal cap
comprising Co, Mo [0078-0079, fig. 5G]. 076 teaches the metal layer is made from PVD
[0080] which is in fact using fluorine free metal(cobalt) deposition process.
Claim 5 is rejected. 076 teaches depositing a metal gap fill material (528) over
the contact capping layer (520) [fig. 5H, 0083].
Claim 6 is rejected as 505 teaches a ratio of t2/t3 is (Mo delivery time to purge
time is 0.07 (when t1 is 0.5 sec, 0046 and purge is 7 sec 0054).
Claim 7 is rejected as 505 teaches the silicon containing gas comprising silane or
disilane [0050].
Claim 8 is rejected as 076 teaches the contact capping layer (520) comprises
molybdenum silicide [0073] and the surface of the contact structure (518)
comprises silicon germanium (SiGe) [0067].
Claim 9 is rejected as 505 teaches molybdenum precursor is molybdenum
pentachloride [0045].
Claim 10 is rejected. 076 teaches a method (for making a semiconductor device)
comprising: forming a contact capping layer (520) over inner surfaces of a cavity (516)
of a semiconductor substrate comprising a surface of a contact structure wherein the
inner surfaces comprising a surface of a contact structure (518) within the cavity [fig.
5D], sidewall of the cavity [fig. 5D], and a bottom surface of the cavity [fig. 5F], wherein
the contact capping layer (520) comprising molybdenum silicide or ruthenium silicide
and deposited by CVD [0073-0074]. 076 further teaches depositing a metal cap (522) selectively on a surface of the contact capping layer (520) within the cavity [fig. 5H, 0079], which in fact can act as a seeding layer on surface of capping layer for next layer (524). 076 does not teach the detail of deposition process. 505 teaches a method of making metal silicide for semiconductor devices [0002] by CVD or ALD [0035], where the silicide layer (molybdenum) is made by;
(a) initiating a first delivery of a Molybdenum precursor for a first period of time
and halting the first delivery of the Mo precursor for a second period of time (step 108
first cycle) [0040];
(b) initiating a second delivery of the molybdenum precursor for a third period of
time and halting the second delivery of the Mo precursor for a fourth period of time (step
108 the second cycle);
(c) delivering a silicon containing gas for a fifth period of time and halting delivery
of the silicon containing gas for a sixth period of time (step 110) [0047]; and
(d) repeating (a), (b) more time and (c) one or more time (or repeat to achieve
desirable thickness) while flowing hydrogen (hydrogen flow during flowing molybdenum
0040, and silicon 0052, and therefore it flows in steps a, b, and c) wherein the first
period of time, the third period of time and the firth period of time do not overlap (505
teaches purging step between precursor delivery step and silicon reactant delivery
steps 0028 therefore they do not overlap). Therefore, it would have been obvious to one
of ordinary skill in the art at the time of the invention was made to have a method of
making semiconductor device as 076 teaches where the metal silicide layer is made by
method of 505, because it teaches suitable method for depositing metal (Mo)silicide for
making semiconductive devices. 505 teaches following carrier gas (inert gas) and molybdenum precursor gas together, but does not clearly teach flowing silicon precursor and carrier (inert gas). However, it is known in the art to have precursor gas and reactant gas flow in chamber with a carrier gas (inert gas) in atomic layer deposition process. For example, 396 teaches forming a metal silicide (MoSi) with ALD where the molybdenum precursor and silicon precursor flow the chamber by carrier (inert gas) [ 0057-0058, 0072]. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention was made to have a method of making semiconductor device as 076, and 505 teach, where silicon precursor also introduces to chamber with carrier(inert) gas, because it is suitable way to introduce reactant gas to ALD chamber. Therefore, when inert gas flows for purging molybdenum precursor, halting time (fourth period), and silicon containing gas added to the inert gas and delivering time (fifth period) happens during it.
Claim 11 is rejected as 505 teaches the silicon containing gas comprising silane
or disilane [0050].
Claim 12 is rejected as 505 teaches the fifth period of time occurs during the
fourth period of time (purging in one area of moving substrate while the other area is
under reaction gas) [0028 last 3 lines].
Claim 13 is rejected as 505 teaches ratio of t1 to t2 is 0.07 (when t1 is 0.5 sec,
0046 and purge is 7 sec 0054).
Claim 14 is rejected as 505 teaches ratio of t3 to t4(Mo and purge for second
cycle) is 0.07 (when t1 is 0.5 sec, 0046 and purge is 7 sec 0054).
Claim 15 is rejected as 505 teaches ratio of t4 to t6(silicon and purge) is (when
t4 is 0.5 sec, 0053 and purge is 0.5 sec 0054).
Claim 16 is rejected. 505 teaches a ratio between the fourth period of time
(second pause time) and the fifth period of time (silicon precursor delivery time) is
1 (purge and silicon) [see claim 15 rejections above].
Claim 18 is rejected. 076 teaches depositing a metal gap fill material (528) over
the contact capping layer (518) [fig. 5H, 0083].
Claim 19 is rejected as 076 teaches the contact capping layer (520) comprises
molybdenum silicide [0073] and the surface of the contact structure (518) comprises
silicon germanium (SiGe) [0067].
Claim 20 is rejected as 505 teaches molybdenum precursor is molybdenum
pentachloride [0045].
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Nicolas L. Breil et al (U. S. Patent Application: 2024/0014076 here after 076), Jiyeon Kim (U. S. Patent Application: 2024/0218505, here after 505), S. Jeon et al (U. S. Patent Application: 2025/0199396, here after 396), further in view of Gaurav Thareja et al (U. S. Patent Application: 2020/0203481, here after 481).
Claim 3 is rejected. 076 teaches metal layer (522) [0079], but does not teach the
thickness of it. 481 teaches formation of metal cap layer (224) on the silicide layer (209,
or 222) [0035. Fig. 3], where thickness of metal cap layer is about thickness of the
silicide layer [fig. 3, fig. 2D], and where the thickness of silicide layer is about thickness
of doped semiconductor layer (220) which is 0.1-20 nm [0030, fig. 2D]. Therefore, it
would have been obvious to one of ordinary skill in the art at the time of the invention
was made to have a method of making semiconductor device as 076 teaches, where
the thickness of metal layer is 0.1-20 nm, because it is suitable thickness for metal layer
on cap layer. Although it does not teach the metal cap has an average thickness
between 5 and 11 nm. However, overlapping ranges are prima facie evidence of
obviousness. It would have been obvious to one having ordinary skill in the art to have
selected the portion of [overlapping range] that corresponds to the claimed range. In re
Malagari, 182 USPQ 549 (CCPA 1974). Therefore, it would have been obvious to one
of ordinary skill in the art at the time of the invention was made to have a method of
making semiconductor device as 076, 505, 396, and 481 teaches where the thickness of metal cap layer is 5-11 nm, because an ordinary skill in the art can have selected the
portion of overlapping range that corresponds to the claimed range in absence of
criticality.
Claim 4 is rejected as 076 teaches depositing a metal gap fill material (528) on
the metal cap (522) [fig. 5G, 0083].
Response to Arguments
Applicant's arguments filed 05/21/26 have been fully considered but they are not persuasive. The applicant argues Kim does not teach sequential schemes of introducing silicon precursor, molybdenum precursor and halting. The examiner disagrees, as Kim teaches ALD process of MoSi, it is inherent that the deposition is repeated and purging(halting) is done after each precursor and reactant flowing.
The applicant argument regarding formation of metal cap layer as seed layer is not persuasive, the cap layer can act as a seed layer for barrier layer not the metal layer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TABASSOM TADAYYON ESLAMI whose telephone number is (571)270-1885. The examiner can normally be reached M-F 9:30-6.
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/TABASSOM TADAYYON ESLAMI/Primary Examiner, Art Unit 1718
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