Prosecution Insights
Last updated: October 01, 2026
Application No. 18/590,102

METHODS OF FORMING LOW RESISTIVITY FILMS USING Microwave treatment

Non-Final OA §102
Filed
Feb 28, 2024
Examiner
PAGE, STEVEN MITCHELL CHR
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Applied Materials Inc.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
387 granted / 463 resolved
+15.6% vs TC avg
Moderate +9% lift
Without
With
+8.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
24 currently pending
Career history
477
Total Applications
across all art units

Statute-Specific Performance

§101
3.8%
-36.2% vs TC avg
§103
38.9%
-1.1% vs TC avg
§102
35.6%
-4.4% vs TC avg
§112
20.6%
-19.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 463 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of the method of claims 1-10 and 20-29 in the reply filed on 07/22/2026 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-10 and 20-29 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by HONDA et al. (US 20130189838 A1, hereinafter Honda) With regards to claim 1, Honda discloses a method (FIGS. 1-5B) comprising: exposing a semiconductor device structure (device shown in in at least FIG. 5B) to a microwave process to cause impurities within at least one electrical connection formed in at least one feature of the semiconductor device structure to rise to a surface of the at least one electrical connection; (Paragraph [0063]: “In this embodiment, when a microwave is radiated when the conductive film 212 is deposited, the impurities adhering onto the conductive film 211 are activated by the microwave,” where the impurities being “activated” moves them to the surface of the conductive film 211) and exposing the semiconductor device structure to a reactive gas to remove the impurities from the surface of the at least one electrical connection. (Paragraph [0063]: “a reducing gas contained in a raw material gas is activated by the microwave and reacts with the impurities, or a metallic element contained in a raw material gas is activated by the microwave, functions as a catalyst, reacts with the impurities, and evaporates the impurities.”) With regards to claim 2, Honda discloses the e method of claim 1, wherein the at least one electrical connection comprises a conductive material deposited within the at least one feature. (conductive material 211, see FIG. 5B) With regards to claim 3, Honda discloses the method of claim 2, wherein the conductive material comprises ruthenium (Ru). (Paragraph [0060]: “it is possible to use a metal film, a half metal film, or a metal alloy film containing at least one selected from…Ru,”) With regards to claim 4, Honda discloses the method of claim 3, wherein the impurities comprise carbon (C), iodine (I), and combinations thereof. (Paragraph [0063]: “…a raw material gas may contain a lot of impurities such as oxygen, carbon…”) With regards to claim 5, Honda discloses the method of claim 1, wherein the reactive gas comprises hydrogen. (Paragraph [0018]: “…hydrogen (H2) gas (reducing gas)…”) With regards to claim 6, Honda discloses the method of claim 1, wherein the impurities further comprise an oxide layer formed on the surface of the electrical connection. (when the conductive film 212 is deposited by a CVD method, a raw material gas may contain a lot of impurities such as oxygen, carbon, fluorine, chlorine, nitrogen, and water.” Thus the impurities can contain, for example, nitrogen oxide) With regards to claim 7, Honda discloses the method of claim 1, wherein the semiconductor device structure comprises a dielectric layer (dielectric 231) formed on a frontside of a device substrate and the semiconductor device structure is patterned to form the at least one feature, wherein the at least one feature extends between a field region of the dielectric layer to a backside of the device substrate. (see FIG. 5B) With regards to claim 8, Honda discloses the method of claim 7, wherein the at least one electrical connection is formed within the at least one feature and extends between the frontside of the device substrate and the backside of the device substrate. (see FIG. 5B) With regards to claim 9, Honda discloses the method of claim 1, wherein the exposing a semiconductor device structure to a microwave process and the exposing the semiconductor device structure to a reactive gas are performed in a same processing chamber. (see paragraph [0063] and FIG. 2) With regards to claim 10, Honda discloses the method of claim 1, wherein the exposing a semiconductor device structure to a microwave process and the exposing the semiconductor device structure to a reactive gas are performed in different processing chambers. (see paragraph [0063] and FIG. 3, showing different chambers.) With regards to claim 20, Honda discloses a method (FIGS. 1-5B) comprising: exposing a semiconductor device structure (device shown in in at least FIG. 5B) to microwaves, wherein exposing the semiconductor device structure to microwaves causes impurities in an electrical connection comprising ruthenium (Ru) to diffuse to a surface of electrical connection; (Paragraph [0063]: “In this embodiment, when a microwave is radiated when the conductive film 212 is deposited, the impurities adhering onto the conductive film 211 are activated by the microwave,” where the impurities being “activated” moves them to the surface of the conductive film 211, Paragraph [0060]: “it is possible to use a metal film, a half metal film, or a metal alloy film containing at least one selected from…Ru,”) and removing at least a portion of the impurities by exposing the semiconductor device structure to a hydrogen containing gas. (Paragraph [0063]: “a reducing gas contained in a raw material gas is activated by the microwave and reacts with the impurities, or a metallic element contained in a raw material gas is activated by the microwave, functions as a catalyst, reacts with the impurities, and evaporates the impurities.” Paragraph [0018]: “…hydrogen (H2) gas (reducing gas)…”) With regards to claim 21, Honda discloses the method of claim 20, wherein the impurities comprise carbon (C), iodine (I), and combinations thereof. (Paragraph [0063]: “…a raw material gas may contain a lot of impurities such as oxygen, carbon…”) With regards to claim 22, Honda discloses the method of claim 20, wherein the impurities further comprise an oxide layer formed on the surface of the electrical connection. (when the conductive film 212 is deposited by a CVD method, a raw material gas may contain a lot of impurities such as oxygen, carbon, fluorine, chlorine, nitrogen, and water.” Thus the impurities can contain, for example, nitrogen oxide) With regards to claim 23, Honda discloses the method of claim 20, wherein the semiconductor device structure comprises a dielectric layer (dielectric 231) formed on a frontside of a device substrate and the semiconductor device structure is patterned to form a feature, wherein the feature extends between a field region of the dielectric layer to a backside of the device substrate. (see FIG. 5B) With regards to claim 24, Honda discloses the method of claim 23, wherein the electrical connection is formed within the feature and extends between the frontside of the device substrate and the backside of the device substrate. (see FIG. 5B) With regards to claim 25, Honda discloses the method of claim 20, wherein the exposing a semiconductor device structure to microwaves and the exposing the semiconductor device structure to the hydrogen containing gas are performed in the same processing chamber. (see paragraph [0063] and FIG. 2) With regards to claim 26, Honda discloses the method of claim 20, wherein the exposing a semiconductor device structure to microwaves and the exposing the semiconductor device structure to a hydrogen containing gas are performed in different processing chambers. (see paragraph [0063] and FIG. 3, showing different chambers.) With regards to claim 27, Honda discloses a method comprising: exposing a semiconductor device structure to microwaves, wherein exposing the semiconductor device structure to microwaves causes impurities in an electrical connection comprising ruthenium (Ru) that is formed in a feature of the semiconductor device structure to diffuse to a surface of electrical connection; (Paragraph [0063]: “In this embodiment, when a microwave is radiated when the conductive film 212 is deposited, the impurities adhering onto the conductive film 211 are activated by the microwave,” where the impurities being “activated” moves them to the surface of the conductive film 211, Paragraph [0060]: “it is possible to use a metal film, a half metal film, or a metal alloy film containing at least one selected from…Ru,”) and exposing the semiconductor device structure to hydrogen to remove the impurities from the surface of the electrical connection, (Paragraph [0063]: “a reducing gas contained in a raw material gas is activated by the microwave and reacts with the impurities, or a metallic element contained in a raw material gas is activated by the microwave, functions as a catalyst, reacts with the impurities, and evaporates the impurities.” Paragraph [0018]: “…hydrogen (H2) gas (reducing gas)…”) wherein: the exposing a semiconductor device structure to microwaves and the exposing the semiconductor device structure to hydrogen are performed in one or more processing chambers. (see paragraph [0063] and FIG. 2, showing one chamber) With regards to claim 28, Honda discloses the method of claim 27, wherein the exposing a semiconductor device structure to a microwave process and the exposing the semiconductor device structure to hydrogen are performed in a same processing chamber. (see paragraph [0063] and FIG. 2) With regards to claim 29, Honda discloses the method of claim 27, wherein the exposing a semiconductor device structure to a microwave process and the exposing the semiconductor device structure to a reactive gas are performed in different processing chambers. (see paragraph [0063] and FIG. 3, showing different chambers.) Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Feb 28, 2024
Application Filed
Aug 10, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
92%
With Interview (+8.7%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 463 resolved cases by this examiner. Grant probability derived from career allowance rate.

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